Problem
In docs/supported_devices.md, the "Adding a New Device" section (step 3) says:
Compile it with OpenVAF to produce an .osdi module
Reference it in a VACASK .sim netlist with load "your_model.osdi"
This is incorrect. The CircuitEngine processes .va Verilog-A source files directly, not pre-compiled .osdi modules. The engine compiles VA files on-the-fly via openvaf_py.
Evidence:
vajax/analysis/engine.py:488-536 — _resolve_load_statements() explicitly handles load "mymodel.va" paths; stems are extracted as model names from .va filenames
docs/getting_started.md — shows the correct format: load "spice/resistor.va"
vendor/VACASK/benchmark/*/vacask/runme.sim — all use load "path/to/model.va"
Fix
Step 3 in supported_devices.md should read:
Reference it in a VACASK .sim netlist with load "your_model.va"
The step about separately compiling to .osdi should be removed — OpenVAF compilation is handled automatically by the engine during parse().