[HDL] Signed vs. Unsigned Multiplication in VHDL/Verilog

[Jiahui17]

The HW implementations of unsigned and 2's complement multiplication are different.

Currently, the VHDL implementation interprets any multiplication as signed multiplication:

The Verilog implementation interprets any multiplication as unsigned multiplication:

• In the VHDL case, the result would be incorrect for unsigned multiplication if any input number is greater than half the maximum possible number
• In the Verilog case, the result would be incorrect if any operand is negative