From 8347e9eb5940809203e771938c908b5d952fc124 Mon Sep 17 00:00:00 2001 From: Nicholas McNeill Date: Fri, 27 Feb 2026 22:03:44 -0500 Subject: [PATCH] Added SPI One Pager --- docs/ip-briefs/IO_SPI_Brief(v1.0).md | 39 ++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 docs/ip-briefs/IO_SPI_Brief(v1.0).md diff --git a/docs/ip-briefs/IO_SPI_Brief(v1.0).md b/docs/ip-briefs/IO_SPI_Brief(v1.0).md new file mode 100644 index 0000000..11608cc --- /dev/null +++ b/docs/ip-briefs/IO_SPI_Brief(v1.0).md @@ -0,0 +1,39 @@ +# SPI - Module Brief (v1.0) + +**Owner:** Nicholas McNeill +**RTL:** rtl/io/spi.sv + +Purpose & Role: +The Serial Peripheral Interface (SPI) is a high speed, 4-wire, full-duplex communication protocol used for short distance data exchange between microcontrollers and peripherals. It uses a shared clock signal to synchronize data transfer. + +Parameters (Registers) & Signals: +Resides on the AXI-Lite Interconnect bus, in a Master (CPU) to Slave (SPI) configuration. All register reads and writes are performed through AXI-Lite signals. + +| Name | Addr. | Default Val | Purpose | +| --- | --- | --- | --- | +| SPDR (Data register) | 000 | R/W 0x00 | Holds the byte to be transmitted or the byte just recieved | +| SPCR (Control Register) | 001 | R/W 0x00 | Enables SPI< selects master/slave mode, and sets clock polarity | +| SPSR (Status Register) | 010 | R/W 0x02 | Indicates transfer completion, write collisions, and mode faults. | +| SPBR (Baud Rate Register) | 011 | R/W 0x02 | Sets the clock frequency divider for the SCK signal. | +| CSCR (Chip Select Register) | 100 | R/w 0xFF | **Manages multiple Slave Select lines for peripheral addressing.** | +| Signal | Dir | Size | Description | +| clk_o | Out | 1b | Serial Clock generated by the Master to synchronize data. | +| Mosi_o | Out | 1b | Master Output, Slave Input; carries data from SoC to peripheral. | +| Miso_i | In | 1b | Master Input, Slave Output; carries data from peripheral to SoC. | +| Ss_n_o | Out | 4b | Slave Select (Active Low) to enable specific external devices. | +| Axi_lite_\* | M<->S | Var | Standard AXI-Lite bus signals (AWADDR, WDATA, RDATA, etc.) for register access. | +| Irq_o | Out | 1b | Interrupt request sent to CPU upon transfer completion or error. | + +Configurations: +Clock Modes: Supports all four SPI modes defined by CPOL and CPHA to ensure compatibility with various peripheral timing requirements.Master/Slave: Primarily configured as a Master in SoC environments, but can be toggled to Slave mode via the SPCR.Baud Rate: The sclk_o frequency is derived by dividing the system clock by the value in SPBR.AXI-Lite valid/ready signals are required for internal register stability before data is shifted out to the physical SPI lines. + +Behavior & Timing: +Timing is strictly governed by clk_o. Data is shifted out and shifted in simultaneously during every clock cycle. To reduce CPU overhead, 16-byte Rx/Tx FIFOs are utilized. Interrupts are triggered when Rx reaches a threshold or the Tx is empty. + +Errors & Dependencies: +Erros are managed by irq_o. Several errors can occur; write collision, mode fault, dependencies, or GPIO. + +Dependencies are the CPU/software driver for hardware interaction in correcting errors or resetting status flags. Reset and known clock signals are also dependent for UART to function properly. If utilizing modem for loopback/flow control with no dedicated pins, then GPIO pins are necessary. + +Performance Targets: +Up to 50 Mhz. 0% Frequency drift. \ No newline at end of file