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[openpowerwtf]

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[Shahed-ur-Rahman]

make -C obj_dir_$mod -f V$mod.mk V$mod
make: Entering directory '/home/shahed/a2o/dev/sim/verilator/obj_dir_soc'
g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-overloaded-virtual -Wno-shadow -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Os -c -o tb_litex_soc.o ../tb_litex_soc.cpp
../tb_litex_soc.cpp:36:10: fatal error: Vsoc_iuq_rn_map__A24.h: No such file or directory
36 | #include "Vsoc_iuq_rn_map__A24.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [Vsoc.mk:61: tb_litex_soc.o] Error 1
make: Leaving directory '/home/shahed/a2o/dev/sim/verilator/obj_dir_soc'
(base) shahed@Shahed:~/a2o/dev/sim/verilator$ grep -R "iuq_rn_map" soc.v

**Getting this error while checking the full soc simulation. Can you please expalain the problem why this file header is missing after litex generation?

[openpowerwtf]

No idea - no earlier errors? iuq_rn_map.v is a source file.