This project is about implementing and simulating a basic 16-bit computer using Verilog HDL on XILINX FPGA architecture, that have its own instruction set and hardwired control unit.
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For project guidelines see Guidelines/
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For more information about implementation see pdfs Report_1 / Report_2
- Hardwired control unit with 34 instructions
- Arithmetic Logic Unit performs 32 operations
- ALU Flag registers: Zero/Carry/Negative/Overflow
- General purpose registers
- General knowledge about computer organization
- Working with registers, ALU's and hardwired control unit
- Implementing relevant control signals for instructions
