APU DMC sample reads should stall the CPU for up to 4 cycles.

[TheDreadedAndy]

In original hardware, sample reads in the APU DMC unit can stall the CPU for up to 4 cycles. The implementation of this stall can cause MMIO reads to effectively happen twice. These double reads can result in incorrect behavior, such as a double controller read causing a missed user input.

Documentation of this issue can be found here and here.