Verilator 5.043 hangs at run time on this test

[svenka3]

Trying this example on latest Verilator (built from source).

Verilator version:

- V e r i l a t i o n   R e p o r t: Verilator 5.043 devel rev v5.042-114-gb9b6eb6 (mod)

First observation - on a 8 GB RAM, 4 core laptop (CentOS 7.9), it takes about 10 minutes to compile/elab. Is this expected? I felt it is lot for the given example, but will try a bigger machine later.

- Verilator: Built from 13.123 MB sources in 371 modules, into 25.211 MB in 2437 C++ files needing 12.202 MB
- Verilator: Walltime 703.944 s (elab=1.523, cvt=8.652, bld=691.968); cpu 13.260 s on 2 threads; alloced 514.113 MB
./obj_dir/Vtbench_top +UVM_TESTNAME=sig_model_test +UVM_PHASE_TRACE +UVM_VERBOSITY=UVM_DEBUG 

Now the main issue - test is hanging and does not seem to enter run_phase, see:

UVM_WARNING /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/base/uvm_root.svh(549) @ 0: reporter [NO_DPI_USED] We are thinking of removing support for UVM_NO_DPI.  Please try this test without it and evaluate the impact
UVM_INFO /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/base/uvm_root.svh(552) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test sig_model_test...
UVM_INFO sig_sequence.svh(6) @ 0: reporter [seq] Starting sig_sequence
UVM_INFO sig_model_test.svh(19) @ 0: uvm_test_top [uvm_test_top] connect_phase 
UVM_INFO /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/base/uvm_traversal.svh(345) @ 0: reporter [UVM/COMP/NAMECHECK] This implementation of the component name checks requires DPI to be enabled
UVM_WARNING /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/base/uvm_traversal.svh(314) @ 0: reporter [NO_VISIT_CHECK] Because UVM_REGEX_NO_DPI is defined, no uvm component name constraints will be checked
UVM_INFO sig_model_test.svh(24) @ 0: uvm_test_top [uvm_test_top] start_of_simulation_phase 
UVM_INFO /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/seq/uvm_sequencer_base.svh(1462) @ 0: uvm_test_top.env.sig_agnt_d.sequencer [PHASESEQ] No default phase sequence for phase 'run'
UVM_INFO /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/seq/uvm_sequencer_base.svh(1462) @ 0: uvm_test_top.env.sig_agnt_m.sequencer [PHASESEQ] No default phase sequence for phase 'run'
UVM_INFO /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/seq/uvm_sequencer_base.svh(1462) @ 0: uvm_test_top.env.sig_agnt_d.sequencer [PHASESEQ] No default phase sequence for phase 'pre_reset'
UVM_INFO /home/srini/tools/chips_a_uvm_vlt_bcl/uvm-verilator/src/seq/uvm_sequencer_base.svh(1462) @ 0: uvm_test_top.env.sig_agnt_m.sequencer [PHASESEQ] No default phase sequence for phase 'pre_reset'

I don't see any run_phase messages (added few prints).

Any hints please?

[svenka3]

Quick update - similar result (hang) on a Mac, though the compile/elab is significantly better.

[kbieganski]

Interesting, it works in CI here on latest Verilator, even with the phase trace flag. Compile times are also better there - a little less than 2 minutes (1 minute on my laptop).

What version of Z3 are you using?
Can you try Verilator v0.42?

As for the compile times, try adding --output-groups $(nproc) to the Verilator command.

[svenka3]

z3 --version

Z3 version 4.12.2 - 64 bit

Not sure if moving to older version is an option, will check. Thanks

[svenka3]

After reading through Verilator scheduling related issues (around same error), I am able to work-around it as follows:

   `ifdef VERILATOR
   always @(posedge clk) begin
     ivif_enable <= ivif.enable;
     ovif_enable <= ovif.enable;
     ovif.enable <= ivif_enable;
     ivif.enable <= ovif_enable;
   end
   `else
     assign ovif.enable = ivif.enable;
   `endif // VERILATOR

I am not claiming it is functionally matching, my aim is to get some UVM test fully running for now.

[kbieganski]

If you gather any more info, feel free to open a new issue in the Verilator repo.

[svenka3]

Revisiting this as I got similar feedback from other expert UVM users as well recently.

Interesting, it works [in CI here on latest Verilator](https://github.com/antmicro/verilator-uvm-example/actions/runs/19833171696/job/56824029814

I took a closer look and your CI test actually is failing - it exits at time 0, I see a warning as:

UVM_WARNING @ 0: run_objection [OBJTN_CLEAR] Object 'uvm_top' cleared objection counts for run_objection

Is this a known issue with some threading/scheduling?

Thanks

[kbieganski]

Thanks, we'll investigate

[techaarvam]

Hi Srinivasan,

You had asked for the logs in the linkedin discussion. Here they are. I just realized its 5.045. I havent paid a close attention to the original issue. Posting the summary report FWIW here. thanks (Travelling, will look closely next week, if this stays open. thanks)

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO : 316
UVM_WARNING : 9
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[DRVCONNECT] 1
[NO_DPI_TSTNAME] 1
[OBJTN_CLEAR] 1
[RNTST] 1
[UVM/COMP/NAME] 7
[UVM/COMP/NAMECHECK] 1
[UVM/RELNOTES] 1
[uvm_test_top] 2
[uvm_test_top.env] 2
[uvm_test_top.env.apb_master_agent] 2
[uvm_test_top.env.apb_master_agent.apb_master_tb_driver] 304
[uvm_test_top.env.apb_master_agent.apb_master_tb_monitor] 2

• /home/rambala/tools/uvm/src/base/uvm_root.svh:587: Verilog $finish
  clock is running
• S i m u l a t i o n R e p o r t: Verilator 5.045 devel
• Verilator: $finish at 100us; walltime 0.004 s; speed 26.101 ms/s
• Verilator: cpu 0.004 s on 1 threads; allocated 19 MB
  ((pyenv1)) ~/work/learn/apb_v2 % verilator -version
  Verilator 5.045 devel rev v5.044-70-gc4dcdeab9

[techaarvam]

Here is another run where there where the actual APB DMA transfer had completed.
I hadnt cared earlier why its running till 3000000 although objections are dropped, but whatever I had dont, I dont have a 0ns issue here.

TA_DBG: psel = 0, penable = 0
TA_DBG: psel = 0, penable = 0
clock is running
clock is running
2995000 nrst=1 valid=0 ready=0
2995000 state=0 psel0=0 penable0=0 pready0=0
2995000 v=0 r=0 psel0=0 pready0=0 psel1=0 pready1=0
2995000 st=0 valid=0 ready=0 | psel0=0 psel1=0 penable0=0 penable1=0 | pready0=0 pready1=0 | mux_pready=0
TA_DBG: psel = 0, penable = 0
TA_DBG: psel = 0, penable = 0
UVM_INFO /home/rambala/tools/uvm/src/base/uvm_report_server.svh(864) @ 3000000: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO : 120
UVM_WARNING : 9
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[DRVCONNECT] 1
[NO_DPI_TSTNAME] 1
[OBJTN_CLEAR] 1
[RNTST] 1
[UVM/COMP/NAME] 7
[UVM/COMP/NAMECHECK] 1
[UVM/RELNOTES] 1
[uvm_test_top] 2
[uvm_test_top.env] 2
[uvm_test_top.env.apb_master_agent] 2
[uvm_test_top.env.apb_master_agent.apb_master_tb_driver] 108
[uvm_test_top.env.apb_master_agent.apb_master_tb_monitor] 2

• /home/rambala/tools/uvm/src/base/uvm_root.svh:587: Verilog $finish
  clock is running
• S i m u l a t i o n R e p o r t: Verilator 5.045 devel
• Verilator: $finish at 100us; walltime 0.004 s; speed 25.638 ms/s
• Verilator: cpu 0.004 s on 1 threads; allocated 19 MB