Early termination with Verilator v.5044

[MikeOpenHWGroup]

Using Verilator v.5042, this environment compiled, and the simulation ran to the expected completion. However, with v5.044, the testbench compiles, but terminates at t=5ps with a UVM_WARNING @ 0: run_objection [OBJTN_CLEAR] Object 'uvm_top' cleared objection counts for run_objection logger message. It appears to be a sheduling issue as the environment components have not yet had a chance to raise any objections.

This is the tail-end of the logfile running with v.5042. All good.

UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: a Received length: a are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 6 Received length: 6 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: a Received length: a are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 9 Received length: 9 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 3 Received length: 3 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 6 Received length: 6 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 7 Received length: 7 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 9 Received length: 9 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 1 Received length: 1 are the same.
UVM_INFO /home/mike/GitHubRepos/antmicro/verilator-uvm-example/main_test_with_v5.042/sig_scoreboard.svh(33) @ 765: uvm_test_top.env.sig_scb [sig_scoreboard] Sent length: 4 Received length: 4 are the same.
UVM_INFO /opt/accellera/1800.2-2017-1.0/src/base/uvm_report_server.svh(864) @ 765: reporter [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   14
UVM_WARNING :   55
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[NO_DPI_TSTNAME]     1
[RNTST]     1
[UVM/COMP/NAME]    55
[UVM/COMP/NAMECHECK]     1
[UVM/RELNOTES]     1
[sig_scoreboard]    10

- /opt/accellera/1800.2-2017-1.0/src/base/uvm_root.svh:585: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.042 2025-11-02
- Verilator: $finish at 770ps; walltime 0.088 s; speed 21.343 ns/s
- Verilator: cpu 0.036 s on 1 threads; alloced 60 MB

This is the logfile running with v.5044. Terminates at t=0.

UVM_WARNING @ 0: run_objection [OBJTN_CLEAR] Object 'uvm_top' cleared objection counts for run_objection
UVM_INFO /opt/accellera/1800.2-2017-1.0/src/base/uvm_report_server.svh(864) @ 0: reporter [UVM/REPORT/SERVER] 
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :    4
UVM_WARNING :   56
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[NO_DPI_TSTNAME]     1
[OBJTN_CLEAR]     1
[RNTST]     1
[UVM/COMP/NAME]    55
[UVM/COMP/NAMECHECK]     1
[UVM/RELNOTES]     1

- /opt/accellera/1800.2-2017-1.0/src/base/uvm_root.svh:585: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.044 2026-01-01
- Verilator: $finish at 5ps; walltime 0.037 s; speed 344.834 ps/s
- Verilator: cpu 0.014 s on 1 threads; alloced 20 MB

[arunvthampi]

Hi @MikeOpenHWGroup ,

I too tried with same readme. But its showing me this error. Kindly do tell if I need to add anything more

[MikeOpenHWGroup]

Yes, I get the same UVM_WARNINGS. However that is a separate issue from the one being discussed here. (Having said that, I should have mentioned it.) If you allow the simulation to run to completion, you should see the same early termination.

[arunvthampi]

But all I could see would be these warnings

[MikeOpenHWGroup]

Did the simulation run to completion? If you can, please attach your logfile.

[kbieganski]

Thanks for reporting, I think this is the same as #29? We're addressing the issue.

[MikeOpenHWGroup]

It certainly looks like it could be the same issue. I would be willing to test that if a patch were available.

[kbieganski]

verilator/verilator#6891 should fix this.

[MikeOpenHWGroup]

Hi @kbieganski, I just built Verilator 5.045 devel rev v5.044-218-gcf1de0b9a and the test now runs to completion. Nice work! Unless you object, I would like to keep this open until the next "announced release". That is likely to be v5.046 in early March.

[kbieganski]

Thanks. I'm not sure I see why this should remain open until next release?

[MikeOpenHWGroup]

I'm not sure I see why this should remain open until next release?

Just being paranoid. 😜