Progress Report & Reference: MLIR Dialect for Hardware-Level SPMW #536
jifengwu2k
started this conversation in
General
Replies: 1 comment
-
|
First you would have to set up a bunch of environment variables. I was using a Conda environment, so I first installed the following in the Conda environment: Then I set up the following environment variables: Then I basically followed Circt's official compilation instructions. Note Circt is a monorepo, it has a full LLVM submodule in it. |
Beta Was this translation helpful? Give feedback.
0 replies
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Uh oh!
There was an error while loading. Please reload this page.
Uh oh!
There was an error while loading. Please reload this page.
-
This is intended as a living document to record my progress, lessons learned, and useful reference materials related to developing an MLIR dialect for hardware-level SPMW. By using the issue in this way, we can easily share updates, document our findings, and support collaboration within the team.
Update: 2026-02-09
I have looked through the implementation of circt-opt.cpp. It seems like circt-opt only supports a hardcoded list consisting of built-in dialects, and not arbitrary user-defined dialects. Furthermore, the Verilog emitter implemented in ExportVerilog.cpp only supports the Comb, Debug, Emit, HW, LTL, OM, SV dialects. This means that we would need to implement our own binaries that lower our dialect to these dialects to work with the rest of Circt.
Update: 2026-02-08
The Debug dialect is built following standard MLIR conventions. Its implementation uses TableGen for declarative specification, C++ for custom logic.
TableGen Files
These describe the declarative portions of the dialect:
DebugDialect.tdDefines the dialect's properties (name:
"dbg", summary, namespace, etc.) and extra methods for ops/types registration.DebugOps.tdDeclares the key IR operations provided by the dialect:
dbg.scope- defines a debug scopedbg.variable- marks a value to be tracked in debug infodbg.struct- aggregates values into a structdbg.array- aggregates values into an arraySpecifies operands, results, custom assembly formats, and documentation.
DebugTypes.tdDeclares the custom types the dialect introduces:
ScopeTypeStructTypeArrayTypeDebug.tdIncludes all the above together, forming the dialect's full TableGen definition. Only this file is directly involved in file generation.
Generated Files (inc/cpp.inc) (not directly authored, but referenced)
DebugDialect.h.inc, DebugDialect.cpp.inc, Debug.h.inc, Debug.cpp.inc, DebugTypes.h.inc, DebugTypes.cpp.inc.tdfiles.Dialect Header/Implementation Files
DebugDialect.hDebugOps.hDebugTypes.hDebugDialect.cppinitialize()(registering custom ops/types).DebugOps.cppdbg.structanddbg.arrayhave custom assembly format logic).DebugDialect::registerOps()).DebugTypes.cppDebugDialect::registerTypes()).Suppose your dialect is called
foo.Write TableGen Descriptions
Write C++ Headers
Write C++ Sources
Use Your Dialect
Update: 2026-02-07
By analyzing the build graph, I have tracked all the dependencies of
circt-opt:As for the headers used for compiling the object files:
LLVM Object Files
MLIR Object Files
CIRCT Object Files
From this point of view, LLVM is a subproject of MLIR, which itself is a subproject of CIRCT.
I have also analyzed the filesystem structure of a dialect:
Progress Report: 2026-02-02
Summary
This week's focus was on infrastructure setup and understanding CIRCT build systems and workflows.
What I Did
1. Repository Creation
Set up a central place for all artifacts related to the SPMW MLIR dialect development. Link: https://github.com/jw2858/MLIR-SPMW-Dialect
2. Compiling and Analyzing CIRCT
Build Graph Construction and Analysis
Developed a Python-based tool, split into several scripts, for build graph construction and analysis:
Scripts and Their Functionality:
01_construct_build_graph.py
cc,c++) and archive (ar) commands.networkx.DiGraphwhere nodes are files and edges are dependencies.build-graph.json02_construct_file_path_trie.py
file-path-trie.pkl03_construct_paths_to_relpaths.py
paths-to-relpaths.json04_construct_relpath_build_graph.py
relpath-build-graph.json05_analyze_extensions.py
.o,.a, binaries, etc.)target-extensions-to-targets-to-sources.json)3. CIRCT Documentation Review
Typical CIRCT Workflow
Define Circuits in MLIR:
hwdialect (for modules, ports, wires)combdialect (for combinational logic)Example:
Optimize:
circt-opt:--canonicalize--cse(common subexpression elimination)--inline--comb-int-range-narrowing--comb-balance-mux--hw-flatten-modulescirct-opt --helpConvert & Simulate:
circt-opt output.mlir --export-verilog -o /dev/null > output.vcirct-optserves as a central entrypoint both for working with dialects and as a focus for dependency analysis, since it links against all CIRCT dialects.4. Work in Progress
circt-opt.Progress Report: 2026-01-27
Timeframe: Past week
What I did
Explored Relevant Codebases
Gained Preliminary Understanding of MLIR Python Bindings
Gained Preliminary Understanding of MLIR Dialect Implementation in C++
mlir-tblgento generate C++ headers.CMAKE_PREFIX_PATH.Takeaways
Plans & Next Steps
Reference: MLIR Dialect Project Structure
A typical MLIR dialect project (following the examples/standalone template) is organized as follows:
Beta Was this translation helpful? Give feedback.
All reactions