Cell.bib

% =======================================================
%           Cell Design Summary 
% =======================================================
%{{{
@article{CELL-TSM2004-Wang,
    title     = {Standard cell layout with regular contact placement},
    author    = {Wang, Jun and Wong, Alfred K. and Lam, Edmund Y.},
    journal   = tsm,
    volume    = {17},
    number    = {3},
    pages     = {375--383},
    year      = {2004},
    publisher = {IEEE},
}
@inproceedings{CELL-VLSIT2011-Northrop,
    title     = {Design technology co-optimization in technology definition for 22nm and beyond},
    author    = {Northrop, Greg},
    booktitle = vlsit,
    pages     = {112--113},
    year      = {2011},
    abstract  = {MOL},
}
@inproceedings{CELL-DAC2013-Mallik,
    title     = {{TEASE}: a systematic analysis framework for early evaluation of {FinFET}-based advanced technology nodes},
    author    = {Mallik, Arindam and Zuber, Paul and Liu, Tsung-Te and Chava, Bharani and Ballal, Bhavana and Del Bario, Pablo Royer and Baert, Rogier and Croes, Kris and Ryckaert, Julien and Badaroglu, Mustafa and others},
    booktitle = dac,
    pages     = {24:1--24:6},
    year      = {2013},
    abstract  = {MOL},
}
@inproceedings{CELL-IRPS2013-Kauerauf,
    title     = {Reliability of {MOL} local interconnects},
    author    = {Kauerauf, Thomas and Branka, Anna and Sorrentino, Giuseppe and Roussel, Philippe and Demuynck, Steven and Croes, Kristof and Mercha, Karim and Bommels, J. and Tokei, Zsolt and Groeseneken, Guido},
    booktitle = irps,
    pages     = {2F--5},
    year      = {2013},
}
@inproceedings{CELL-IEDM2013-Rashed, 
    title     = {Innovations in special constructs for standard cell libraries in sub 28nm technologies}, 
    author    = {Rashed, M. and Jain, N. and Kim, J. and Tarabbia, M. and Rahim, I and Ahmed, S. and Kim, J. and others},
    booktitle = iedm,
    year      = {2013}, 
    pages     = {9.7.1--9.7.4}, 
    abstract  = {MOL},
}
@inproceedings{CELL-CICC2014-Ryckaert,
    title     = {Design technology co-optimization for {N10}},
    author    = {Ryckaert, Julien and Raghavan, Praveen and Baert, Rogier and Bardon, Marie Garcia and Dusa, M. and others},
    booktitle = cicc,
    pages     = {1--8},
    year      = {2014},
}
@inproceedings{CELL-SPIE2015-Xu,
    title     = {A Systematic Framework for Evaluating Cell Level Middle-Of-Line {(MOL)} Robustness for Multiple Patterning},
    author    = {Xiaoqing Xu and Brian Cline and Greg Yeric and Bei Yu and David Z.~Pan},
    booktitle = spie,
    volume    = {9427},
    year      = {2015},
}
@article{CELL-JM3-2016-Xu,
    title   = {Systematic framework for evaluating standard cell middle-of-line robustness for multiple patterning lithography},
    author  = {Xu, Xiaoqing and Cline, Brian and Yeric, Greg and Yu, Bei and Pan, David Z.},
    journal = jm3,
    volume  = {15},
    number  = {2},
    pages   = {021202--021202},
    year    = {2016},
}
@inproceedings{CELL-ISPD2015-Martins,
    title     ={Open cell library in 15nm {FreePDK} technology},
    author    ={Martins, Mayler and Matos, Jody Maick and Ribas, Renato P and Reis, Andr{\'e} and Schlinker, Guilherme and Rech, Lucio and Michelsen, Jens},
    booktitle =ispd,
    pages     ={171--178},
    year      ={2015},
}
@article{CELL-MEJO2016-Clark,
    title     = {{ASAP7}: A 7-nm finFET predictive process design kit},
    author    = {Clark, Lawrence T and Vashishtha, Vinay and Shifren, Lucian and Gujja, Aditya and Sinha, Saurabh and Cline, Brian and Ramamurthy, Chandarasekaran and Yeric, Greg},
    journal   = mejo,
    volume    = {53},
    pages     = {105--115},
    year      = {2016},
    publisher = {Elsevier}
}
% ==== multi-row height cells
@misc{CELL-USP2005-Gheewala,
  title  = {Dual-height cell with variable width power rail architecture},
  author = {Gheewala, Tushar R. and Colwell, Michael J. and Yang, Henry H. and Breid, Duane G.},
  year   = {2005},
  month  = jan # "~4",
  note   = {{US Patent 6,838,713}},
}
@misc{CELL-USP2014-Sherlekar,
  title  = {Cell architecture for increasing transistor size},
  author = {Sherlekar, Deepak D.},
  year   = {2014},
  month  = jan # "~14",
  note   = {{US Patent 8,631,374}},
}
@inproceedings{CELL-SPIE2008-Baek,
  title     = {Ultra-high density standard cell library using multi-height cell structure},
  author    = {Baek, Sang-Hoon and Kim, Ha-Young and Lee, Young-Keun and Jin, Duck-Yang and Park, Se-Chang and Cho, Jun-Dong},
  booktitle = spie,
  volume    = {7268},
  year      = {2008},
}
%}}}

% ==== 1D synthesis 
%{{{
@inproceedings{CELL-ICCAD1988-Stauffer,
    title     = {Optimal CMOS cell transistor placement: a relaxation approach},
    author    = {Stauffer, Andre and Nair, Ravi},
    booktitle = iccad,
    pages     = {364--367},
    year      = {1988},
}
@article{CELL-TCAD1989-Bar-Yehuda,
    title    = {Depth-first-search and dynamic programming algorithms for efficient {CMOS} cell generation},
    author   = {Bar-Yehuda, Reuven and Feldman, Jack A and Pinter, Ron Y and Wimer, Shmuel},
    journal  = tcad,
    volume   = {8},
    number   = {7},
    pages    = {737--743},
    year     = {1989},
}
@inproceedings{CELL-DAC1997-Guruswamy,
    title     = {{CELLERITY}: A fully automatic layout synthesis system for standard cell libraries},
    author    = {Guruswamy, Mohan and Maziasz, Robert L and Dulitz, Daniel and Raman, Srilata and Chiluvuri, Venkat and Fernandez, Andrea and Jones, Larry G},
    booktitle = dac,
    pages     = {327--332},
    year      = {1997},
}
@inproceedings{CELL-DAC2005-Kheterpal,
    title     = {Design methodology for {IC} manufacturability based on regular logic-bricks},
    author    = {Kheterpal, Veerbhan and Rovner, Vyacheslav and Hersan, Thiago G. and Motiani, Dipti and Takegawa, Yoichi and Strojwas, Andrzej J. and Pileggi, Larry},
    booktitle = dac,
    pages     = {353--358},
    year      = {2005},
}
@inproceedings{CELL-DAC2007-Taylor,
    title     = {Exact combinatorial optimization methods for physical design of regular logic bricks},
    author    = {Taylor, Brian and Pileggi, Larry},
    booktitle = dac,
    pages     = {344--349},
    year      = {2007},
}
@inproceedings{CELL-DAC2007-Maly,
    title     = {{OPC}-free and minimally irregular {IC} design style},
    author    = {Maly, Wojciech and Lin, Yi-Wei and Marek-Sadowska, Malgorzata},
    booktitle = dac,
    pages     = {954--957},
    year      = {2007},
}
@inproceedings{CELL-ASPDAC2010-Zhang,
    title     = {On process-aware {1-D} standard cell design},
    author    = {Hongbo Zhang and Martin D.~F.~Wong and Chao, Kai-Yuan},
    booktitle = aspdac,
    pages     = {838--842},
    year      = {2010},
}
@article{CELL-TCAD2010-Jhaveri,
    title     = {Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings},
    author    = {Tejas Jhaveri and Vyacheslav Rovner and Lars Liebmann and Larry Pileggi and Andrzej J.~Strojwas and Jason D.~Hibbeler},
    journal   = tcad,
    pages     = {509--527},
    year      = {2010},
    volume    = {29},
    number    = {4},
    publisher = {IEEE},
}
@inproceedings{CELL-SPIE2012-vaid,
    title     = {Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node},
    author    = {Vaidyanathan, Kaushik and Ng, Siew Hoon and Morris, Daniel and Lafferty, Neal and Liebmann, Lars and others},
    booktitle = spie,
    volume    = {8327},
    year      = {2012},
}
@inproceedings{CELL-SPIE2013-Vaid,
    title     = {Rethinking {ASIC} design with next generation lithography and process integration},
    author    = {Vaidyanathan, Kaushik and Liu, Renzhi and Liebmann, Lars and Lai, Kafai and Strojwas, Andrzej and Pileggi, Larry},
    booktitle = spie,
    volume    = {8684},
    year      = {2013},
}
@article{CELL-TCAD2013-Wu,
    title     = {{1-D} Cell Generation With Printability Enhancement},
    author    = {Wu, Po-Hsun and Lin, MP and Chen, Tung-Chieh and Ho, Tsung-Yi and Chen, Yu-Chuan and Siao, Shun-Ren and Lin, Shu-Hung},
    journal   = tcad,
    volume    = {32},
    number    = {3},
    pages     = {419--432},
    year      = {2013},
}
@article{CELL-TCAD2013-Cortadella,
    title    = {Area-Optimal Transistor Folding for {1-D} Gridded Cell Design},
    author   = {Cortadella, Jordi},
    journal  = tcad,
    volume   = {32},
    number   = {11},
    pages    = {1708--1721},
    year     = {2013},
    abstract = {},
}
@article{CELL-TCAD2014-Cortadella,
    title   = {A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing.},
    author  = {Cortadella, Jordi and Petit, Jordi and G{\'o}mez, Sergio and Moll, Francesc},
    journal = tcad,
    volume  = {33},
    number  = {3},
    pages   = {409--422},
    year    = {2014},
}
@inproceedings{CELL-SPIE2015-Chava,
    title     = {Standard cell design in {N7: EUV} vs.~immersion},
    author    = {Chava, Bharani and Rio, David and Sherazi, Yasser and Trivkovic, Darko and Gillijns, Werner and Debacker, Peter and Raghavan, Praveen and Elsaid, Ahmad and Dusa, Mircea and Mercha, Abdelkarim and others},
    booktitle = spie,
    volume    = 9427,
    year      = {2015},
    abstract  = {IMEC},
}
@inproceedings{CELL-DATE2015-Lu,
    title     = {Simultaneous transistor pairing and placement for {CMOS} standard cells},
    author    = {Lu, Ang and Lu, Hsueh-Ju and Jang, En-Jang and Lin, Yu-Po and Hung, Chun-Hsiang and Chuang, Chun-Chih and Lin, Rung-Bin},
    booktitle = date,
    pages     = {1647--1652},
    year      = {2015},
}
@inproceedings{CELL-GLSVLSI2015-Ye,
    title     = {Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line},
    author    = {Wei Ye and Bei Yu and Yong-Chan Ban and Lars Liebmann and David Z.~Pan},
    booktitle = glsvlsi,
    pages     = {289--294},
    year      = {2015},
}
@inproceedings{CELL-ISPD2016-Ryckaert,
    title     = {Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue},
    author    = {Ryckaert, Julien},
    booktitle = ispd,
    pages     = {89--89},
    year      = {2016},
}
@article{CELL-JM3-2016-Sherazi,
    title    = {Architectural strategies in standard-cell design for the 7 nm and beyond technology node},
    author   = {Sherazi, Syed Muhammad Yasser and Chava, Bharani and Debacker, Peter and others},
    journal  = jm3,
    volume   = {15},
    number   = {1},
    pages    = {013507--013507},
    year     = {2016},
    abstract = {IMEC},
}
@inproceedings{CELL-ISPD2017-Cremer,
    title     = {Automatic Cell Layout in the 7nm Era},
    author    = {Cremer, Pascal and Hougardy, Stefan and Schneider, Jan and Silvanus, Jannik},
    booktitle = ispd, 
    pages     = {99--106},
    year      = {2017},
}
@inproceedings{CELL-GLSVLSI2017-Vidal,
    title     = {Under-the-Cell Routing to Improve Manufacturability},
    author    = {Vidal-Obiols, Alex and Cortadella, Jordi and Petit, Jordi},
    booktitle = glsvlsi,
    pages     = {125--130},
    year      = {2017},
}
%}}}

% ==== 2D Synthesis
%{{{
@article{CELL-TODAES2003-Riepe,
    title     = {Transistor placement for noncomplementary digital {VLSI} cell synthesis},
    author    = {Riepe, Michael A and Sakallah, Karem A},
    journal   = todaes,
    volume    = {8},
    number    = {1},
    pages     = {81--107},
    year      = {2003},
    publisher = {ACM},
}
@inproceedings{CELL-DAC2011-Ryzhenko,
    title     = {Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries},
    author    = {Ryzhenko, Nikolai and Burns, Steven},
    booktitle = dac,
    pages     = {83--88},
    year      = {2011},
}
@inproceedings{CELL-DAC2012-Ryzhenko,
    title     = {Standard cell routing via Boolean satisfiability},
    author    = {Ryzhenko, Nikolai and Burns, Steven},
    booktitle = dac,
    pages     = {603--612},
    year      = {2012},
}
@inproceedings{CELL-ASPDAC2013-Hougardy,
    title     = {{BonnCell}: Automatic layout of leaf cells},
    author    = {Hougardy, Stefan and Nieberg, Tim and Schneider, Jan},
    booktitle = aspdac,
    pages     = {453--460},
    year      = {2013},
}
@inproceedings{CELL-DATE2016-Lu,
    title     = {Practical {ILP}-based routing of standard cells},
    author    = {Lu, Hsueh-Ju and Jang, En-Jang and Lu, Ang and Zhang, Yu Ting and Chang, Yu-He and Lin, Chi-Hung and Lin, Rung-Bin},
    booktitle = date,
    pages     = {245--248},
    year      = {2016},
}
@inproceedings{CELL-ASPDAC2018-Jo,
    title     = {Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion}, 
    author    = {K. Jo and S. Ahn and T. Kim and K. Choi}, 
    booktitle = aspdac,
    pages     = {500--506}, 
    year      = {2018}, 
}
%}}}

% ==== Layout Migration
%{{{
@inproceedings{CELL-DAC1983-Liao,
    title     = {An algorithm to compact a {VLSI} symbolic layout with mixed constraints},
    author    = {Liao, Yuh-Zen and Wong, Chak-Kuen},
    booktitle = dac,
    pages     = {107--112},
    year      = {1983},
    abstract  = {longest-path},
}
@article{CELL-TCAD1987-Lee,
    title     = {{VLSI} layout compaction with grid and mixed constraints},
    author    = {Lee, Jin-Fuw and Tang, Donald T},
    journal   = tcad,
    volume    = {6},
    number    = {5},
    pages     = {903--910},
    year      = {1987},
    publisher = {IEEE},
    abstract  = {constraint graph, Mixed ILP, longest-path based method},
}
@inproceedings{CELL-ISPD1997-Heng,
    title     = {{A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation}},
    author    = {Heng, Fook-Luen and Chen, Zhan and Tellez, Gustavo E},
    booktitle = ispd,
    pages     = {116--121},
    year      = {1997},
}
@inproceedings{CELL-ISPD2005-Yuan,
    title     = {Technology migration technique for designs with strong {RET}-driven layout restrictions},
    author    = {Yuan, Xin and McCullen, Kevin W and Heng, Fook-Luen and Walker, Robert F and Hibbeler, Jason and Allen, Robert J and Narayan, Rani R},
    booktitle = ispd,
    pages     = {175--182},
    year      = {2005},
    abstract  = {2-stage: heuristic + LP},
}
@article{CELL-TCAD2005-Zhu,
    title   = {Calligrapher: a new layout-migration engine for hard intellectual property libraries},
    author  = {Zhu, Jianwen and Fang, Fang and Tang, Qianying},
    journal = tcad,
    volume  = {24},
    number  = {9},
    pages   = {1347--1361},
    year    = {2005},
}
@inproceedings{CELL-ICCAD2006-Tang,
    title     = {Technology migration techniques for simplified layouts with restrictive design rules},
    author    = {Tang, Xiaoping and Yuan, Xin},
    booktitle = iccad,
    pages     = {655--660},
    year      = {2006},
}
@inproceedings{CELL-DAC2013-Salodkar,
    title     = {Automatic design rule correction in presence of multiple grids and track patterns},
    author    = {Salodkar, Nitin and Rajagopalan, Subramanian and Bhattacharya, Sambuddha and Batterywala, Shabbir},
    booktitle = dac,
    pages     = {26:1--26:6},
    year      = {2013},
    abstract  = {LP with unimodularity},
}
@inproceedings{CELL-ISPD2014-Xu,
    title     = {Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization},
    author    = {Xiaoqing Xu and Brian Cline and Greg Yeric and Bei Yu and David Z.~Pan},
    pages     = {101--108},
    booktitle = ispd,
    year      = {2014},
}
@article{CELL-TCAD2015-Xu,
    title     = {Self-aligned double patterning aware pin access and standard cell layout co-optimization},
    author    = {Xu, Xiaoqing and Cline, Brian and Yeric, Greg and Yu, Bei and Pan, David Z.},
    journal   = tcad,
    volume    = {34},
    number    = {5},
    pages     = {699--712},
    year      = {2015},
    publisher = {IEEE},
}
%}}}

% ==== Cell Characterization
%{{{
@inproceedings{CELL-SPIE2007-Ma,
    title     = {Line Edge Roughness Impact on Critical Dimension Variation},
    author    = {Y.~Ma and H.~Levinson and Thomas Wallow},
    booktitle = spie,
    volume    = 6518,
    year      = {2007},
}
@inproceedings{CELL-SPIE2009-Ban,
    title     = {Electrical Impact of Line-Edge Roughness on Sub-45nm Node Standard Cell},
    author    = {Yongchan Ban and Savithri Sundareswaran and Rajendran Panda and David Z.~Pan},
    booktitle = spie,
    year      = {2009},
}
@inproceedings{CELL-SPIE2010-Ban,
    title     = {Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell},
    author    = {Ban, Yongchan and Ma, Yuansheng and Levinson, Harry J and Deng, Yunfei and Kye, Jongwook and Pan, David Z.},
    booktitle = spie,
    volume    = 7641,
    year      = {2010},
}
@inproceedings{CELL-ISPD2010-Ban,
    title     = {Total Sensitivity Based {DFM} Optimization of Standard Library Cells},
    author    = {Yongchan Ban and S.~Sundareswaran and David Z.~Pan},
    booktitle = ispd,
    pages     = {113--120},
    year      = {2010},
} 
@inproceedings{CELL-DAC2010-Ban,
    title     = {Compact Modeling and Robust Layout Optimization for Contacts in Deep Subwavelength Lithography},
    author    = {Yongchan Ban and David Z.~Pan},
    booktitle = dac,
    pages     = {408--411},
    year      = {2010},
} 
@inproceedings{CELL-SPIE2011-Chin,
    title     = {Variability aware timing models at the standard cell level},
    author    = {Eric Y.~Chin and Cooper S.~Levy and Andrew R.~Neureuther},
    booktitle = spie,
    volume    = {7641},
    year      = {2010},
}
@article{CELL-JETCAS2011-Ban,
    title   = {Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization}, 
    author  = {Yongchan Ban and Pan, D.~Z.}, 
    journal = jetcas,
    month   = {june}, 
    volume  = {1}, 
    number  = {2}, 
    pages   = {150--159},
    year    = {2011}, 
}
@INPROCEEDINGS{CELL-DAC2011-Ban, 
    title     = {Layout aware line-edge roughness modeling and poly optimization for leakage minimization}, 
    author    = {Ban, Yongchan and Yang, Jae-Seok}, 
    booktitle = dac,
    pages     = {447--452},
    year      = {2011}, 
}
%}}}