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%===============Testing=======================
@inproceedings{TEST-DAC1979-Grason,
title = {{TMEAS}, a testability measurement program},
author = {Grason, John},
booktitle = dac,
pages = {156--161},
year = {1979},
}
@inproceedings{TEST-DAC1980-Goldstein,
title = {{SCOAP}: Sandia controllability/observability analysis program},
author = {Goldstein, Lawrence H and Thigpen, Evelyn L},
booktitle = dac,
pages = {190--196},
year = {1980},
}
@inproceedings{TEST-ATS1997-Xu,
title = {Testability prediction for sequential circuits using neural networks},
author = {Xu, Shiyi and Dias, G Percy and Waignjo, Peter and Shi, Bole},
booktitle = ats,
pages = {48--53},
year = {1997},
}
@inproceedings{TEST-NORCHIP1997-Larsson,
title = {Early Prediction of Testability by Analyzing Behavioral {VHDL} Specifications},
author = {Larsson, Erik and Peng, Zebo},
booktitle = {Proceedings of the NORCHIP Conference},
pages = {259--266},
year = {1997}
}
@inproceedings{TEST-DSD2006-Pecenka,
title = {Testability estimation based on controllability and observability parameters},
author = {Pecenka, Tomas and Strnadel, Josef and Kot{\'a}sek, Zdenek and Sekanina, Luk{\'a}s},
booktitle = {EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools},
pages = {504--514},
year = {2006},
}
@article{TEST-TODAES2008-Pecenka,
title = {Evolution of synthetic {RTL} benchmark circuits with predefined testability},
author = {Pecenka, Tomas and Sekanina, Lukas and Kotasek, Zdenek},
journal = todaes,
volume = {13},
number = {3},
pages = {54},
year = {2008},
publisher = {ACM}
}
@inproceedings{TEST-ITC2009-Ren,
title = {Low cost test point insertion without using extra registers for high performance design},
author = {Ren, Haoxing and Kusko, Mary and Kravets, Victor and Yaari, Rona},
booktitle = itc,
pages = {1--8},
year = {2009},
}
@article{TEST-TOC2012-Yang,
title = {Test point insertion with control points driven by existing functional flip-flops},
author = {Yang, Joon-Sung and Touba, Nur A and Nadeau-Dostie, Benoit and others},
journal = toc,
volume = {61},
number = {10},
pages = {1473--1483},
year = {2012},
}
@inproceedings{TEST-ITC2015-Li,
title = {Efficient observation-point insertion for diagnosability enhancement in digital circuits},
author = {Li, Zipeng and Goel, Sandeep Kumar and Lee, Frank and Chakrabarty, Krishnendu},
booktitle = itc,
pages = {1--10},
year = {2015},
}
@inproceedings{TEST-VTS2016-He,
title = {Test-point insertion efficiency analysis for LBIST applications},
author = {He, Miao Tony and Contreras, Gustavo K and Tehranipoor, Mark and Tran, Dat and Winemberg, LeRoy},
booktitle = vts,
pages = {1--6},
year = {2016},
}
@inproceedings{TEST-ITC2018-Liu,
title = {Back-End Layout Reflection for Test Chip Design},
author = {Zeye Liu and Ronald D. Blanton},
booktitle = itc,
year = {2018},
}
@article{TEST-TCAD2018-Tang,
title = {Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits},
author = {Tang, Xiaofeng and Xu, Aiqiang and Li, Ruifeng and Zhu, Min and Dai, Jinling},
journal = tcad,
volume = {37},
number = {7},
pages = {1483--1493},
year = {2018},
publisher = {IEEE},
}
@inproceedings{TEST-DAC2019-Ma,
title = {High Performance Graph Convolutional Networks with Applications in Testability Analysis},
author = {Ma, Yuzhe and Ren, Haoxing and Khailany, Brucek and Sikka, Harbinder and Luo, Lijuan and Natarajan, Karthikeyan and Yu, Bei},
booktitle = dac,
pages = {18:1--18:6},
year = {2019},
}