ERROR: Cell type 'PCLKDIV' instantiated as 'U$$0' is not supported by this device.

[slagernate]

Seems Yosys/Prjoxide doesn't recognize the following primitive (found in the Radiant FPGA Libraries Reference Guide docs/web page), although Radiant does:

        m.submodules += Instance("PCLKDIV", 
                                 p_DIV_PCLKDIV      = "X2",
                                 i_CLKIN            = clk48.i,
                                 i_LSRPDIV          = Const(0),
                                 o_CLKOUT           = clk_ser,
                                 )

Would love to help "document" this if I was pointed in the right direction.