From abe2cd69a3f2f6d656eb59b10ae5ccde17093cd7 Mon Sep 17 00:00:00 2001 From: Vincent Esche Date: Sat, 2 Dec 2023 18:45:05 +0100 Subject: [PATCH 1/2] Add DRC rules for PCBWay --- PCBWay/PCBWay.kicad_dru | 169 +++++++++++++++++++++++ PCBWay/PCBWay.kicad_pcb | 79 +++++++++++ PCBWay/PCBWay.kicad_pro | 298 ++++++++++++++++++++++++++++++++++++++++ PCBWay/PCBWay.kicad_sch | 5 + PCBWay/README.md | 1 + 5 files changed, 552 insertions(+) create mode 100644 PCBWay/PCBWay.kicad_dru create mode 100644 PCBWay/PCBWay.kicad_pcb create mode 100644 PCBWay/PCBWay.kicad_pro create mode 100644 PCBWay/PCBWay.kicad_sch create mode 100644 PCBWay/README.md diff --git a/PCBWay/PCBWay.kicad_dru b/PCBWay/PCBWay.kicad_dru new file mode 100644 index 0000000..94378fc --- /dev/null +++ b/PCBWay/PCBWay.kicad_dru @@ -0,0 +1,169 @@ +(version 1) +#PCBWay Custom DRC for Kicad 7 + +# ----------------------------------- Minimum trace width and spacing (PICK ONE) -------------------- + +# 2oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (innner layer)" +#(constraint track_width (min 0.1524mm)) +#(constraint clearance (min 0.1778mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + + +# 2-layer, 1oz copper +(rule "Minimum Trace Width and Spacing (outer layer)" +(constraint track_width (min 0.127mm)) +(constraint clearance (min 0.127mm)) +(layer outer) +(condition "A.Type == 'track'")) + +(rule "Minimum Trace Width and Spacing (inner layer)" +(constraint track_width (min 0.1mm)) +(constraint clearance (min 0.1mm)) +(layer inner) +(condition "A.Type == 'track'")) + +# 4-layer , 1oz and 0.5oz copper +#(rule "Minimum Trace Width and Spacing (outer layer)" +#(constraint track_width (min 0.09mm)) +#(constraint clearance (min 0.09mm)) +#(layer outer) +#(condition "A.Type == 'track'")) + +#(rule "Minimum Trace Width and Spacing (inner layer)" +#(constraint track_width (min 0.1mm)) +#(constraint clearance (min 0.09mm)) +#(layer inner) +#(condition "A.Type == 'track'")) + +# ------------------------------------------------------------------------------------------------------ + +# Drill/hole size - listed here to maintain order of rule application. Must not override rule set in Via hole/diameter size below. +(rule "drill hole size (mechanical)" +(constraint hole_size (min 0.15mm) (max 6.3mm))) + +# ----------------------------------- Via hole/diameter size (PICK ONE) ------------------------------------ + +# 2-layer standard +(rule "Minimum Via Diameter and Hole Size" +(constraint hole_size (min 0.3mm)) +(constraint via_diameter (min 0.5mm)) +(condition "A.Type == 'via'")) + +# 4-layer standard +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.3mm)) +#(constraint via_diameter (min 0.45mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.25mm)) +#(constraint via_diameter (min 0.4mm)) +#(constraint disallow buried_via) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.2mm)) +#(constraint via_diameter (min 0.35mm)) +#(condition "A.Type == 'via'")) + +# 4-layer advanced +#(rule "Minimum Via Diameter and Hole Size" +#(constraint hole_size (min 0.15mm)) +#(constraint via_diameter (min 0.3mm)) +#(condition "A.Type == 'via'")) + +# ----------------------------------- Drill/hole size ------------------------------------ + +(rule "PTH Hole Size" +(constraint hole_size (min 0.2mm) (max 6.35mm)) +(condition "A.Type != 'Via' && A.isPlated()")) + +(rule "Minimum Non-plated Hole Size" +(constraint hole_size (min 0.5mm)) +(condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Pad Size" +(constraint hole_size (min 0.5mm)) +(constraint annular_width (min 0.25mm)) +(condition "A.Type == 'Pad' && A.isPlated()")) + +(rule "Minimum Castellated Hole Size" +(constraint hole_size (min 0.6mm)) +(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Min. Plated Slot Width" +(constraint hole_size (min 0.5mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && A.isPlated()")) + +(rule "Min. Non-Plated Slot Width" +(constraint hole_size (min 0.8mm)) +(condition "(A.Hole_Size_X != A.Hole_Size_Y) && !A.isPlated()")) + +# ----------------------------------- Minimum clearance ---------------------------------- +(rule "hole to hole clearance (different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Net != B.Net")) + +(rule "via to track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "via to via clearance (same nets)" +(constraint hole_to_hole (min 0.254mm)) +(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "pad to pad clearance (with hole, different nets)" +(constraint hole_to_hole (min 0.5mm)) +(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "pad to pad clearance (without hole, different nets)" +(constraint clearance (min 0.127mm)) +(condition "A.Type == 'Pad' && B.Type == 'Pad'")) + +(rule "NPTH to Track clearance" +(constraint hole_clearance (min 0.254mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "NPTH with copper around" +(constraint hole_clearance (min 0.20mm)) +(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type != 'track'")) + +(rule "PTH to Track clearance" +(constraint hole_clearance (min 0.33mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +(rule "Pad to Track clearance" +(constraint clearance (min 0.2mm)) +(condition "A.isPlated() && A.Type != 'Via' && B.Type == 'track'")) + +# ----------------------------------- Board Outlines (PICK ONE) ------------------------------------- +#Default Routed Edge Clearance +(rule "Trace to Outline" +(constraint edge_clearance (min 0.3mm)) +(condition "A.Type == 'track'")) + +#Special Clearance for V-Score Edges +#(rule "Trace to V-Cut" +#(constraint edge_clearance (min 0.4mm)) +#(condition "A.Type == 'track'")) + +# ----------------------------------- silkscreen -------------------------- +(rule "Minimum Text" +(constraint text_thickness (min 0.15mm)) +(constraint text_height (min 0.8mm)) +(layer "?.Silkscreen")) + +(rule "Pad to Silkscreen" +(constraint silk_clearance (min 0.15mm)) +(layer outer) +(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) diff --git a/PCBWay/PCBWay.kicad_pcb b/PCBWay/PCBWay.kicad_pcb new file mode 100644 index 0000000..214c44f --- /dev/null +++ b/PCBWay/PCBWay.kicad_pcb @@ -0,0 +1,79 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (solder_mask_min_width 0.1016) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + +) diff --git a/PCBWay/PCBWay.kicad_pro b/PCBWay/PCBWay.kicad_pro new file mode 100644 index 0000000..e2334cd --- /dev/null +++ b/PCBWay/PCBWay.kicad_pro @@ -0,0 +1,298 @@ +{ + "board": { + "3dviewports": [], + "design_settings": { + "defaults": { + "board_outline_line_width": 0.049999999999999996, + "copper_line_width": 0.19999999999999998, + "copper_text_italic": false, + "copper_text_size_h": 1.0, + "copper_text_size_v": 1.0, + "copper_text_thickness": 0.19999999999999998, + "copper_text_upright": false, + "courtyard_line_width": 0.049999999999999996, + "dimension_precision": 4, + "dimension_units": 3, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, + "fab_line_width": 0.09999999999999999, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.09999999999999999, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 0.762, + "height": 1.524, + "width": 1.524 + }, + "silk_line_width": 0.15, + "silk_text_italic": false, + "silk_text_size_h": 0.7999999999999999, + "silk_text_size_v": 0.7999999999999999, + "silk_text_thickness": 0.15, + "silk_text_upright": false, + "zones": { + "min_clearance": 0.5 + } + }, + "diff_pair_dimensions": [ + { + "gap": 0.0, + "via_gap": 0.0, + "width": 0.0 + } + ], + "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "connection_width": "warning", + "copper_edge_clearance": "error", + "copper_sliver": "warning", + "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint": "error", + "footprint_type_mismatch": "ignore", + "hole_clearance": "error", + "hole_near_hole": "error", + "invalid_outline": "error", + "isolated_copper": "warning", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + "padstack": "warning", + "pth_inside_courtyard": "ignore", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_dangling": "warning", + "track_width": "error", + "tracks_crossing": "error", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + "min_clearance": 0.0, + "min_connection": 0.0, + "min_copper_edge_clearance": 0.0, + "min_hole_clearance": 0.254, + "min_hole_to_hole": 0.254, + "min_microvia_diameter": 0.19999999999999998, + "min_microvia_drill": 0.09999999999999999, + "min_resolved_spokes": 2, + "min_silk_clearance": 0.0, + "min_text_height": 0.7999999999999999, + "min_text_thickness": 0.15, + "min_through_hole_diameter": 0.19999999999999998, + "min_track_width": 0.1016, + "min_via_annular_width": 0.1016, + "min_via_diameter": 0.5, + "solder_mask_clearance": 0.0, + "solder_mask_min_width": 0.0, + "solder_mask_to_copper_clearance": 0.0, + "use_height_for_length_calcs": true + }, + "teardrop_options": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 5, + "td_on_pad_in_zone": false, + "td_onpadsmd": true, + "td_onroundshapesonly": false, + "td_ontrackend": false, + "td_onviapad": true + } + ], + "teardrop_parameters": [ + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], + "track_widths": [ + 0.0, + 0.1016, + 0.127, + 0.1524, + 0.2032, + 0.254, + 0.3048, + 0.508, + 0.762 + ], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + }, + { + "diameter": 0.4064, + "drill": 0.2032 + }, + { + "diameter": 0.4572, + "drill": 0.254 + }, + { + "diameter": 0.61, + "drill": 0.3 + } + ], + "zones_allow_external_fillets": false + }, + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "PCBWay.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.1524, + "diff_pair_gap": 0.1524, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.1524, + "line_style": 0, + "microvia_diameter": 0.4572, + "microvia_drill": 0.254, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.1524, + "via_diameter": 0.4572, + "via_drill": 0.254, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.1524, + "diff_pair_gap": 0.1524, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.1524, + "line_style": 0, + "microvia_diameter": 0.4572, + "microvia_drill": 0.254, + "name": "Power_1", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.3048, + "via_diameter": 0.4572, + "via_drill": 0.254, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.1524, + "diff_pair_gap": 0.1524, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.1524, + "line_style": 0, + "microvia_diameter": 0.4572, + "microvia_drill": 0.254, + "name": "Power_2", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.508, + "via_diameter": 0.4572, + "via_drill": 0.254, + "wire_width": 6 + } + ], + "meta": { + "version": 3 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "legacy_lib_dir": "", + "legacy_lib_list": [] + }, + "sheets": [], + "text_variables": {} +} diff --git a/PCBWay/PCBWay.kicad_sch b/PCBWay/PCBWay.kicad_sch new file mode 100644 index 0000000..2e2aa2f --- /dev/null +++ b/PCBWay/PCBWay.kicad_sch @@ -0,0 +1,5 @@ +(kicad_sch (version 20230121) (generator eeschema) + (paper "A4") + (lib_symbols) + (symbol_instances) +) diff --git a/PCBWay/README.md b/PCBWay/README.md new file mode 100644 index 0000000..f5cdd30 --- /dev/null +++ b/PCBWay/README.md @@ -0,0 +1 @@ +# Design Rules for PCBWay From 89cce416f08ddaf21b8161d584f5bde2764b66c8 Mon Sep 17 00:00:00 2001 From: Vincent Esche Date: Sat, 2 Dec 2023 18:45:21 +0100 Subject: [PATCH 2/2] Update root-level 'README.md' file --- README.md | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index 0991f6c..3a48143 100644 --- a/README.md +++ b/README.md @@ -1,21 +1,33 @@ -# JLCPCB-KiCad-DRC +# KiCad-DRC -JLCPCB Design Rules for KiCad 7.0, implemented as Custom Rules in PCB Editor `File > Board_Setup... > Design Rules > Custom Rules`), and stored in the `.kicad_dru` file. +Design Rules for KiCad 7.0, implemented as Custom Rules in PCB Editor `File > Board_Setup... > Design Rules > Custom Rules`), and stored in the `.kicad_dru` file. These rules use some features only available in KiCad 7.0. Each design rule is validated for PASS/FAIL the associated PCB (`.kicad_pcb`). -## Use in your KiCad 7 project +## Manufacturer Rules + +Currently this project provides rule files for the following manufacturers: + +### JLCPCB + +- [Official Capabilities](https://jlcpcb.com/capabilities/pcb-capabilities) +- ~~Official Design Rules~~ -Simply copy the [`JLCPCB.kicad_dru`](JLCPCB/JLCPCB.kicad_dru) file into your KiCad 7 project folder, and rename it to match your project name `your-project.kicad_dru`. +The JLCPCB [rule file](JLCPCB/JLCPCB.kicad_dru) is found at: `JLCPCB/JLCPCB.kicad_dru`. -The JLCPCB Design Rules will automatically be included in the KiCad PCB Editor (`File`>`Board Setup...`>`Design Rules`>`Custom Rules`), and be included when performing a [Design Rules Check (DRC)](https://docs.kicad.org/7.0/en/pcbnew/pcbnew.html#design_rule_checking) (`Ìnspect`>`Design Rules Checker`). +### PCBWay + +- [Official Capabilities](https://www.pcbway.com/capabilities.html) +- [Official Design Rules](https://www.pcbway.com/pcb_prototype/PCB_Design_Rule_Check.html) + +The PCBWay [rule file](PCBWay/PCBWay.kicad_dru) is found at: `PCBWay/PCBWay.kicad_dru`. + +## Use in your KiCad 7 project -## JLCPCB documentation -- [PCB Manufacturing & Assembly Capabilities](https://jlcpcb.com/capabilities/pcb-capabilities) -- [Capabilities](https://jlcpcb.com/capabilities/Eagle%20PCB%20to%20gerber%20files) +Simply pick the manufacturer of your choice and copy the corresponding `/.kicad_dru`(e.g. `JLCPCB/JLCPCB.kicad_dru`) file into your KiCad 7 project folder, and rename it to match your project name, e.g. `your-project.kicad_dru`. -## KiCAD documentation -- [Custom Design Rules (KiCad 7.0)](https://docs.kicad.org/7.0/en/pcbnew/pcbnew.html#custom_design_rules) +The Design Rules will automatically be included in the KiCad PCB Editor (`File`>`Board Setup...`>`Design Rules`>`Custom Rules`), and be included when performing a [Design Rules Check (DRC)](https://docs.kicad.org/7.0/en/pcbnew/pcbnew.html#design_rule_checking) (`Ìnspect`>`Design Rules Checker`). +For more info on how to use custom design rules in KiCad 7.0+ see the correpsonding [KiCAD documentation](https://docs.kicad.org/7.0/en/pcbnew/pcbnew.html#custom_design_rules).