From 6c15d84fa8b0715b9217f45a2e41c7db37627aa2 Mon Sep 17 00:00:00 2001 From: Ioannis Constantinou Date: Wed, 11 Mar 2026 16:54:46 +0200 Subject: [PATCH 1/2] pin_exec_driven: fix Inst_Info lookup aliasing across cores --- src/pin/pin_lib/uop_generator.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/pin/pin_lib/uop_generator.c b/src/pin/pin_lib/uop_generator.c index 19b70e10..c420b00d 100644 --- a/src/pin/pin_lib/uop_generator.c +++ b/src/pin/pin_lib/uop_generator.c @@ -783,6 +783,9 @@ static uns generate_uops(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace_uop void convert_pinuop_to_t_uop(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace_uop) { Flag new_entry = FALSE; Inst_Info* info; + // Keep instruction-cache lookup independent of per-core CMP address tagging. + // The uop cache key should use the original program address bits only. + Addr lookup_addr = convert_to_cmp_addr(0, pi->instruction_addr); // Due to JIT compilation, each branch must be decoded to verify which instruction the PC maps to. // To decrease unnecessary malloc/free, fetch inst_info from hashmap // instead of allocating. However first instruction must be decoded. @@ -797,7 +800,7 @@ void convert_pinuop_to_t_uop(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace info->fake_inst = TRUE; info->fake_inst_reason = pi->fake_inst_reason; } else { - info = cpp_hash_table_access_create(proc_id, pi->instruction_addr, pi->inst_binary_lsb, pi->inst_binary_msb, 0, + info = cpp_hash_table_access_create(proc_id, lookup_addr, pi->inst_binary_lsb, pi->inst_binary_msb, 0, &new_entry); info->fake_inst = FALSE; info->fake_inst_reason = WPNM_NOT_IN_WPNM; @@ -838,7 +841,7 @@ void convert_pinuop_to_t_uop(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace info->fake_inst = TRUE; info->fake_inst_reason = pi->fake_inst_reason; } else { - info = cpp_hash_table_access_create(proc_id, pi->instruction_addr, pi->inst_binary_lsb, pi->inst_binary_msb, + info = cpp_hash_table_access_create(proc_id, lookup_addr, pi->inst_binary_lsb, pi->inst_binary_msb, ii, &new_entry); info->fake_inst = FALSE; @@ -889,14 +892,18 @@ void convert_pinuop_to_t_uop(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace for (ii = 0; ii < num_uop; ii++) { if (ii > 0) { - info = cpp_hash_table_access_create(proc_id, pi->instruction_addr, pi->inst_binary_lsb, pi->inst_binary_msb, ii, + info = cpp_hash_table_access_create(proc_id, lookup_addr, pi->inst_binary_lsb, pi->inst_binary_msb, ii, &new_entry); } ASSERT(proc_id, !new_entry); trace_uop[ii]->info = info; trace_uop[ii]->eom = FALSE; - ASSERT(proc_id, info->addr == pi->instruction_addr); + if (info->addr != pi->instruction_addr) { + // A stale entry can differ only by CMP core bits; rebind it to this core's tagged address. + ASSERT(proc_id, convert_to_cmp_addr(0, info->addr) == convert_to_cmp_addr(0, pi->instruction_addr)); + info->addr = pi->instruction_addr; + } ASSERT(proc_id, info->trace_info.inst_size == pi->size); Flag is_last_uop = (ii == (num_uop - 1)); From 1f9656263b651e336671f2bcc203569b50411876 Mon Sep 17 00:00:00 2001 From: Ioannis Constantinou Date: Thu, 12 Mar 2026 09:52:34 +0200 Subject: [PATCH 2/2] pin_exec_driven: clarify canonical lookup comment --- src/pin/pin_lib/uop_generator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/pin/pin_lib/uop_generator.c b/src/pin/pin_lib/uop_generator.c index c420b00d..5323d0f0 100644 --- a/src/pin/pin_lib/uop_generator.c +++ b/src/pin/pin_lib/uop_generator.c @@ -783,7 +783,7 @@ static uns generate_uops(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace_uop void convert_pinuop_to_t_uop(uns8 proc_id, ctype_pin_inst* pi, Trace_Uop** trace_uop) { Flag new_entry = FALSE; Inst_Info* info; - // Keep instruction-cache lookup independent of per-core CMP address tagging. + // Use canonical address (proc_id=0) for consistent hash key within per-core table. // The uop cache key should use the original program address bits only. Addr lookup_addr = convert_to_cmp_addr(0, pi->instruction_addr); // Due to JIT compilation, each branch must be decoded to verify which instruction the PC maps to.