[regression] Job summary is not printed to CLI on completion #75
Description
dvsim==1.6.0
In-tree DVSIM (failures)
[harry@neptune:~/projects/opentitan]$ util/dvsim/dvsim.py hw/ip/i2c/dv/i2c_sim_cfg.hjson --tool xcelium -i i2c_host_error_intr --fi 1
INFO: [dvsim] [proj_root]: /home/harry/projects/opentitan
INFO: [SimCfg] [scratch_path]: [i2c] [/home/harry/projects/opentitan/scratch/dvsim_migration/i2c-sim-xcelium]
00:00:09 [ run ]: [Q: 0, D: 1, P: 0, F: 0, K: 0, T: 1] 0% i2c:0.i2c_host_error_intr.1 ERROR: [Scheduler] [00:00:12]: [run]: [status] [i2c:0.i2c_host_error_intr.1: F]
00:00:12 [ run ]: [Q: 0, D: 0, P: 0, F: 1, K: 0, T: 1] 100% INFO: [FlowCfg] [results]: [i2c]:
## I2C Simulation Results
### Monday December 01 2025 15:58:49 UTC
### GitHub Revision: [`543cf4b607`](https://github.com/lowrisc/opentitan/tree/543cf4b60774bd58498ff5c6c0ed5a2e879ebfe9)
### Branch: dvsim_migration
### [Testplan](https://opentitan.org/book/hw/ip/i2c/data/i2c_testplan.html)
### Simulator: XCELIUM
### Test Results
| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|:-------:|:---------------:|:--------------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
| V2 | host_error_intr | i2c_host_error_intr | 1.000s | 14.041us | 0 | 1 | 0.00 % |
| V2 | | **TOTAL** | | | 0 | 1 | 0.00 % |
| | | **TOTAL** | | | 0 | 1 | 0.00 % |
## Failure Buckets
* `UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between` has 1 failures:
* Test i2c_host_error_intr has 1 failures.
* 0.i2c_host_error_intr.1\
Line 99, in log /home/harry/projects/opentitan/scratch/dvsim_migration/i2c-sim-xcelium/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 14041237 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 14041237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
INFO: [FlowCfg] [scratch_path]: [i2c] [/home/harry/projects/opentitan/scratch/dvsim_migration/i2c-sim-xcelium]
ERROR: [dvsim] Errors were encountered in this run.
[harry@neptune:~/projects/opentitan]$
lowRISC/dvsim (failures)
[harry@neptune:~/projects/opentitan]$ dvsim hw/ip/i2c/dv/i2c_sim_cfg.hjson --tool xcelium -i i2c_host_error_intr --fi 1
[I 251201 15:58:00 run:840] [proj_root]: /home/harry/projects/opentitan
[I 251201 15:58:00 sim:201] [scratch_path]: [i2c] [/home/harry/projects/opentitan/scratch/dvsim_migration/i2c-sim-xcelium]
00:00:09 [ run ]: [Q: 0, D: 1, P: 0, F: 0, K: 0, T: 1] 0% i2c:0.i2c_host_error_intr.1 [E 251201 15:58:23 scheduler:506] [00:00:11]: [run]: [status] [i2c:0.i2c_host_error_intr.1: F]
00:00:11 [ run ]: [Q: 0, D: 0, P: 0, F: 1, K: 0, T: 1] 100%
[harry@neptune:~/projects/opentitan]$
in-tree dvsim (no failures)
[harry@neptune:~/projects/opentitan]$ util/dvsim/dvsim.py hw/ip/rom_ctrl/dv/rom_ctrl_32kB_sim_cfg.hjson --tool xcelium -i rom_ctrl_smoke
INFO: [dvsim] [proj_root]: /home/harry/projects/opentitan
INFO: [SimCfg] [scratch_path]: [rom_ctrl] [/home/harry/projects/opentitan/scratch/dvsim_migration/rom_ctrl_32kB-sim-xcelium]
00:01:22 [ run ]: [Q: 0, D: 0, P: 2, F: 0, K: 0, T: 2] 100% INFO: [FlowCfg] [results]: [rom_ctrl]:
## ROM_CTRL/32KB Simulation Results
### Monday December 01 2025 16:06:05 UTC
### GitHub Revision: [`543cf4b607`](https://github.com/lowrisc/opentitan/tree/543cf4b60774bd58498ff5c6c0ed5a2e879ebfe9)
### Branch: dvsim_migration
### [Testplan](https://opentitan.org/book/hw/ip/rom_ctrl_32kB/data/rom_ctrl_testplan.html)
### Simulator: XCELIUM
### Test Results
| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|:-------:|:--------------------:|:---------------|:-----------------:|:----------------:|:---------:|:-------:|:-----------:|
| V1 | smoke | rom_ctrl_smoke | 3.000s | 2.137ms | 2 | 2 | 100.00 % |
| V1 | | **TOTAL** | | | 2 | 2 | 100.00 % |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 3.000s | 2.137ms | 2 | 2 | 100.00 % |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 3.000s | 2.137ms | 2 | 2 | 100.00 % |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 3.000s | 2.137ms | 2 | 2 | 100.00 % |
| | | **TOTAL** | | | 2 | 2 | 100.00 % |
INFO: [FlowCfg] [scratch_path]: [rom_ctrl] [/home/harry/projects/opentitan/scratch/dvsim_migration/rom_ctrl_32kB-sim-xcelium]
[harry@neptune:~/projects/opentitan]$
lowRISC/dvsim (no failures)
[harry@neptune:~/projects/opentitan]$ dvsim hw/ip/rom_ctrl/dv/rom_ctrl_32kB_sim_cfg.hjson --tool xcelium -i rom_ctrl_smoke
[I 251201 16:12:55 run:840] [proj_root]: /home/harry/projects/opentitan
[I 251201 16:12:55 sim:201] [scratch_path]: [rom_ctrl] [/home/harry/projects/opentitan/scratch/dvsim_migration/rom_ctrl_32kB-sim-xcelium]
00:00:40 [ run ]: [Q: 0, D: 0, P: 2, F: 0, K: 0, T: 2] 100%
[harry@neptune:~/projects/opentitan]$