mooneye's lcdon_write_timing-GS fails

[Rodrigodd]

I investigated this failed test, but could not reach a conclusion on what the solution is. But I want to document here my investigation.

Analysis of test lcdon_write_timing

This test checks at which points of the PPU timeline a write to OAM and VRAM are blocked or not. They are blocked when the PPU is neither in mode 3 nor in mode 2. It tests by turning on the PPU, waiting N NOP opcodes, and then writing to the memory region.

The test is failing to write to OAM after waiting 9 NOPs when it should succeed. A NOP before or after, the writes fail as expected.

The signal that controls if the OAM is blocked is AJUJ (low if block, high if not). It is a NOR3 between ACYL (high if in mode 2), AJON (high if mode 3), and DMA_RUN.

What appears to be happening is that the test expects that a write that happens when PPU is changing from mode 2 to mode 3 should reach the OAM memory. One way for this to happen is if ACYL falls a little before AJON rises, giving a little pulse on AJUJ, enough to enable the write to OAM memory.

So I checked for the common signal responsible for changing those values. That signal is AVAP (STOP_OAM_PARSING). It resets both the latch that drives ACYL and the latch that drives AJON.

But looking at the path between those signals, it is expected that AJON rises before ACYL, which does not explain the bug:

avap -> OR -> asen -> reset.NOR_LATCH.q -> besu -> AND2 -> acyl -> in2.NOR3 -> ajuj
avap -> reset.NOR_LATCH.nq -> nxymu -> AND2 -> ajon -> in3.NOR3 -> ajuj

avap -> acyl = OR + LATCH + AND2
avap -> ajon = LATCH + AND2

Close up:

[Rodrigodd]

I took a closer look at this. Using the map at https://iceboy.a-singer.de/dmg_cpu_b_map/ and the netlist descriptions at http://iceboy.a-singer.de/doc/dmg_cpu_b_netlist.html#c_ajuj, I made a rough measurement of the length and the number of transistors in the path between AVAP and AJUJ:

Below are the distances between the signals. These measure the direct path
between the cells, but maybe the full size of the entire wire also affects the
timing?

avap -> asen = ~150um (full wire is ~20 times bigger)
in2.asen.y = 2 transistors
asen -> besu = ~700um
r.besu.q = ?? transistors (2?)
besu -> acyl = ~700um
in2.acyl.y = 2 transistors
acyl -> ajuj = ~150um
in2.ajuj.y = 1 or 2 transistor

total = ~7 transistors + 1700um

avap -> nxymu = ~1000um (full wire is ~3 times bigger)
r.nxymu.nq = ?? transistor (2?)
nxymu -> ajon = ~2100um (full wire is ~5 times bigger)
in1.ajon.y = 2 or 3 transistors
ajon -> ajuj = ~120um
in3.ajuj.y = 1 transistor

total = ~5 transistors + 3220um

We can see that the path through AJON is substantially larger than the path through ACYL. So, if that difference in distance causes the ACYL AJON to have a longer delay than AJON ACYL, that would justify the test ROM behavior.

I tried to estimate the signal delay through those wires, but I could not find any easy equation where I could just plug the wire length and it would give me the delay time. I found, for example, the "Elmore delay formula", but I need the values of resistance and capacitance for the wires, but I have no idea for sensible values.

But anyway, If I just ensure that ACYL AJON path have a bigger delay than AJON ACYL in the simulation, the test may start to pass, I will try that when I find time. I hope that timing considerations like those are just exception in the design, they make it harder to get this running in Verilator.

[msinger]

I also don't know how we could come up with a way to calculate the delays based on the wire length. This is information we would need to get from the chip manufacturer. There are multiple things that we can't know, that we would need to know to calculate the resistance and the capacitance. We would need the material (copper or tungsten, or whatever), the thickness, the distance between the layers, and so on.

Also, the size of the transistors are affecting how quickly they can change the charge of a huge wire. Maybe it would be worth checking if the transistors involved in the AJON path are bigger, this would explain how they are able of charging the bigger net quicker.

When I'm done with the CPU, I'd like to update the simulation so it can also be done on transistor level. Then I would also treat PMOS and NMOS transistors differently. PMOS should introduce roughly twice the delay than NMOS transistors. In the CPU they often compensate for that transistor difference by making the PMOS twice as big as the NMOS.

[Rodrigodd]

Just noticed that in my last comment I swapped AJON and ACYL, it is AJON that needs to have a bigger delay than ACYL. So if all transistors in the chip have the same standard size, it makes sense for AJON to have a bigger delay than ACYL, as expected.

[msinger]

Okay, so that means that we have to take the wire size into account as well.

[Rodrigodd]

I tested adding a extra delay for the AJON signal, but it was not enough. There is another path used for putting the cpu bus in the OAM address bus that needs a delay between nxymu and asam, but even then the "render" address is put in the OAM bus before oam_b_ncs do a posedge, which triggers the write.

Looking at the signals dependencies is unlikely that the delay between AJON and oam_b_ncs posedge would be smaller than between AJON and oam_addr_nrender.

I will need to think a bit more to find the explanation of how a write to OAM should happen there.