Generalize `tc_sram` to separate logic requirement from physical implementation

[phsauter]

As mentioned in #14:

The current tc_sram wrapper does not generalize to more than one clock and the ports always come with read and write capabilities. That is a bit too limiting for the memories that are usually available in modern techs.

I would like to add that eg in CVA6 the logic requirements of the memory is mixed with the physical implementation, ie RTL designers already make decisions about how the logic memories should be split into physical SRAMs by partitioning them into multiple tc_sram.
I think this is fundamentally a flawed approach and ideally the logic requirement should be strictly a separate concern from the actual implementation. For this to work the RTL designer ought to instantiate a single tc_sram and communicate the requirements via inputs or parameters. Then the backend engineer can partition this into multiple SRAMs if required while making sure the requirements are fulfilled.

Examples for the communicated logic requirements are eg these 64bit need 8bit accesses, another 64bit don't and the final 32bit need bit level accesses (but all of them always access the same address so they could be in the same SRAM).