Fix bug related to large integer constants

[sgherbst]

Even though Python supports arbitrary-size integers, most Verilog simulators do not. As a result, there can be subtle bugs where integer constants overflow within the simulator, before they are even assigned. This problem could be solved by using an explicit width when formatting large constants (possibly switching to hex as well). Care would need to be taken to make sure the generated Verilog is still fairly readable.