Add fixed width literals.

[tcr]

Currently, you can specify a unfixed width literal with a leading 0:

115 => 115
0d115 => 115
0b1110011 => 115
0x73 => 115

You can specify a bit width by changing "0" to a different leading number, but this information is currently tossed. This should propagate to the final Verilog stage, as so:

115 => 7'd115
7d115 => 7'd115
7b1110011 => 7'b1110011
7x73 => 7'h73

Notably, even bare variables like 115 should be compiled with a bit width as much as possible, given that Verilog's default assumption of 32 bits is probably incorrect for many intents. When a bit width can't be determined or inferred by types, a compilation error should be thrown.