Undeclared `_FSM` reg breaks `sequence`

[kevinmehall]

With the sequence.hdl example, the _FSM variable in the generated Verilog is never declared, so it defaults to a 1-bit wire. This results in it toggling between two states instead of going through the whole sequence. I added a reg [2:0] _FSM = 0; to the generated Verilog and it behaved as expected.

[tcr]

Thanks for catching that @kevinmehall. I snuck some changes into a patch version bump that broke any sequence examples—so I just released 0.5.0 which should fix it.

A __FSM_1 (and 2, etc.) variable should be auto-generated for any fsm or sequence struct now, e.g.

reg [(3)-1:0] __FSM_1 = 0;
...
case (__FSM_1)
  0: begin
    rot <= 1;
    __FSM_1 <= 5;
  end

[tcr]

And happy new year!