feat: Complete MLow Codec IP implementation with comprehensive testing and CI/CD

Major improvements and new features:

🎯 Core Implementation:
- Complete MLow Codec IP with audio interface, encoder, decoder, and packet framer
- Array-based frame buffering with proper handshaking protocols
- Packed array optimizations for Yosys synthesis compatibility
- Verilator-compatible blocking/non-blocking assignments

🧪 Testing Infrastructure:
- Comprehensive SystemVerilog testbenches (basic, comprehensive, Verilator-specific)
- Cocotb Python testbench with multiple test scenarios
- Formal verification with SystemVerilog assertions
- C++ main functions for Verilator integration

🏗️ Synthesis & Analysis:
- ASIC synthesis flow with Yosys and ABC
- FPGA synthesis flow with NextPNR and icepack
- Gate analysis with detailed reporting
- OpenLane integration for advanced ASIC flows

📊 CI/CD & Automation:
- Enhanced GitHub Actions with progress indicators and timeout handling
- Transparent synthesis progress (10-30+ minute operations)
- Comprehensive test coverage reporting
- Automated artifact collection and analysis

🔧 Build System:
- Restructured build directories (build/simulation, build/waveforms, build/logs)
- Proper artifact management with .gitignore
- Enhanced Makefile targets for all flows
- Progress monitoring and timeout protection

📚 Documentation:
- Complete architecture, testbench, and overview documentation
- Waveform analysis and reference documentation
- Comprehensive README with usage examples
- Integration guides for all tools and flows

🛡️ Quality & Reliability:
- Fixed Verilator BLKLOOPINIT and BLKANDNBLK errors
- Resolved Yosys unpacked array syntax issues
- Comprehensive error handling and logging
- Production-ready synthesis flows

All tests pass: SystemVerilog simulation, Cocotb verification, formal checks,
ASIC/FPGA synthesis, and gate analysis. Ready for production use.

Author: shivarammysore

.github/workflows/build-and-test.yml

@@ -2,6 +2,47 @@
 runs/
 results/
 
+# Scripts and documentation
+run_ubuntu.sh           # Ubuntu test script (should not be committed)
+docs/*refs.md          # Reference documentation files
+
+# Build directories
+build/                  # Main build directory
+obj_dir/               # Verilator object directory
+
+# Simulation artifacts (Verilog/SystemVerilog)
+*.vcd                   # Waveform files
+*.vvp                   # Icarus Verilog simulation files
+*.vpd                   # VCS waveform files
+*.wlf                   # ModelSim waveform files
+*.key                   # License key files
+*.log                   # Tool log files
+simv                    # VCS simulation executable
+simv.out               # VCS simulation output
+simv.daidir            # VCS simulation directory
+*.o                    # Object files
+*.a                    # Archive files
+*.so                   # Shared object files
+
+# Testbench build artifacts
+tb/sv_tb/build/        # SystemVerilog testbench build directory
+tb/sv_tb/logs/         # Testbench log files
+tb/sv_tb/waves/        # Testbench waveform files
+tb/cocotb/build/       # Cocotb build directory
+tb/cocotb/logs/        # Cocotb log files
+
+# Synthesis artifacts
+flow/synthesis/netlists/  # Synthesis netlists
+flow/synthesis/reports/   # Synthesis reports
+flow/fpga/build/          # FPGA build directory
+flow/fpga/reports/        # FPGA reports
+flow/yosys/build/         # Yosys build directory
+
+# Coverage files
+coverage/               # Coverage data
+*.ucdb                 # Coverage database files
+*.xml                  # Coverage XML files
+
 # Python (cocotb)
 __pycache__/
 *.py[cod]