From 900a4b35b2f8f86eff3c94209784f579013373e8 Mon Sep 17 00:00:00 2001 From: yomaytk Date: Sat, 14 Feb 2026 10:43:56 +0000 Subject: [PATCH] Fix the several aarch64 instructions tests. --- .gitignore | 6 +- backend/remill/lib/Arch/AArch64/Arch.cpp | 18 +- backend/remill/lib/Arch/AArch64/Decode.cpp | 8 +- .../lib/Arch/AArch64/Semantics/BITBYTE.cpp | 23 ++ .../lib/Arch/AArch64/Semantics/SIMD.cpp | 6 +- .../tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S | 35 +++ .../tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S | 13 ++ .../tests/AArch64/BINARY/FMADD_t_FLOATDP3.S | 34 +-- .../tests/AArch64/BINARY/FMAX_t_FLOATDP2.S | 129 +++++++++++ .../tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S | 25 +++ .../tests/AArch64/BINARY/FNMSUB_t_FLOATDP3.S | 25 +++ .../tests/AArch64/BINARY/FSQRT_t_FLOATDP1.S | 25 +++ .../AArch64/BINARY/UMSUBL_64WA_DP_3SRC.S | 12 + .../tests/AArch64/BITBYTE/CLS_n_DP_1SRC.S | 58 +++++ backend/remill/tests/AArch64/CMakeLists.txt | 6 +- .../AArch64/CONVERT/FCVTAS_nS_FLOAT2INT.S | 12 + .../AArch64/CONVERT/FCVTZS_64S_FLOAT2INT.S | 12 + .../tests/AArch64/CONVERT/FRINTA_t_FLOATDP1.S | 12 + .../tests/AArch64/CONVERT/FRINTM_t_FLOATDP1.S | 25 +++ .../remill/tests/AArch64/DATAXFER/FMOV_NToN.S | 48 +++- .../AArch64/DATAXFER/INS_ASIMDINS_IR_R.S | 56 ++++- .../tests/AArch64/DATAXFER/LD1R_ASISDLSO_R1.S | 103 +++++++++ .../AArch64/DATAXFER/LD1_ASISDLSEP_I1_I1.S | 64 +++++- .../AArch64/DATAXFER/LD1_ASISDLSEP_I2_I2.S | 88 +++++++- .../AArch64/DATAXFER/LD1_ASISDLSEP_I3_I3.S | 80 ++++++- .../AArch64/DATAXFER/LD1_ASISDLSEP_I4_I4.S | 88 +++++++- .../AArch64/DATAXFER/LD1_ASISDLSE_R1_1V.S | 64 +++++- .../AArch64/DATAXFER/LD1_ASISDLSE_R2_2V.S | 72 +++++- .../AArch64/DATAXFER/LD1_ASISDLSE_R3_3V.S | 80 ++++++- .../AArch64/DATAXFER/LD1_ASISDLSE_R4_4V.S | 88 +++++++- .../AArch64/DATAXFER/LD1_ASISDLSOP_SINGLE.S | 131 +++++++++++ .../AArch64/DATAXFER/LD1_ASISDLSO_SINGLE.S | 58 +++++ .../AArch64/DATAXFER/LD2_ASISDLSEP_I2_I.S | 71 +++++- .../tests/AArch64/DATAXFER/LD2_ASISDLSE_R2.S | 71 +++++- .../AArch64/DATAXFER/LDP_n_LDSTPAIR_OFF.S | 90 +++++++- .../AArch64/DATAXFER/LDP_n_LDSTPAIR_POST.S | 71 +++++- .../AArch64/DATAXFER/LDP_n_LDSTPAIR_PRE.S | 73 +++++- backend/remill/tests/AArch64/DATAXFER/LDRB.S | 39 +++- backend/remill/tests/AArch64/DATAXFER/LDRH.S | 40 +++- backend/remill/tests/AArch64/DATAXFER/LDRSB.S | 78 ++++++- backend/remill/tests/AArch64/DATAXFER/LDRSH.S | 82 ++++++- backend/remill/tests/AArch64/DATAXFER/LDRSW.S | 40 +++- .../AArch64/DATAXFER/LDR_n_LDST_IMMPOST.S | 80 ++++++- .../AArch64/DATAXFER/LDR_n_LDST_IMMPRE.S | 78 ++++++- .../tests/AArch64/DATAXFER/LDR_n_LDST_POS.S | 78 ++++++- .../AArch64/DATAXFER/LDUR_FP_LDST_UNSCALED.S | 89 ++++++++ .../AArch64/DATAXFER/LDUR_n_LDST_UNSCALED.S | 44 +++- .../AArch64/DATAXFER/LDXR_LRn_LDSTEXCL.S | 24 +- .../tests/AArch64/DATAXFER/MOVN_n_MOVEWIDE.S | 24 ++ backend/remill/tests/AArch64/DATAXFER/SMOV.S | 50 ++++- .../AArch64/DATAXFER/ST1_ASISDLSEP_I2_I2.S | 88 +++++++- .../AArch64/DATAXFER/ST1_ASISDLSE_R1_1V.S | 64 +++++- .../AArch64/DATAXFER/ST1_ASISDLSE_R2_2V.S | 80 +++++-- .../AArch64/DATAXFER/ST1_ASISDLSOP_SINGLE.S | 117 ++++++++++ .../AArch64/DATAXFER/ST1_ASISDLSO_SINGLE.S | 56 +++++ backend/remill/tests/AArch64/DATAXFER/STLR.S | 11 +- .../AArch64/DATAXFER/STLXR_SRn_LDSTEXCL.S | 8 +- .../tests/AArch64/DATAXFER/STP_FP_LDSTPAIR.S | 95 ++++++++ .../AArch64/DATAXFER/STP_n_LDSTPAIR_OFF.S | 26 ++- backend/remill/tests/AArch64/DATAXFER/STRB.S | 48 ++-- backend/remill/tests/AArch64/DATAXFER/STRH.S | 27 ++- .../tests/AArch64/DATAXFER/STR_FP_LDST.S | 170 ++++++++++++++ .../AArch64/DATAXFER/STR_n_LDST_IMMPOST.S | 26 ++- .../AArch64/DATAXFER/STR_n_LDST_IMMPRE.S | 36 ++- .../tests/AArch64/DATAXFER/STR_n_LDST_POS.S | 76 +++++-- .../AArch64/DATAXFER/STUR_FP_LDST_UNSCALED.S | 78 +++++++ backend/remill/tests/AArch64/DATAXFER/UMOV.S | 40 +++- .../tests/AArch64/LOGICAL/ASRV_n_DP_2SRC.S | 27 +++ .../tests/AArch64/LOGICAL/LSLV_n_DP_2SRC.S | 27 +++ .../tests/AArch64/LOGICAL/LSRV_n_DP_2SRC.S | 27 +++ .../tests/AArch64/LOGICAL/RORV_n_DP_2SRC.S | 27 +++ backend/remill/tests/AArch64/Run.cpp | 7 + .../tests/AArch64/SIMD/ADDP_ASIMDSAME_ONLY.S | 70 ++++++ .../tests/AArch64/SIMD/ADDP_ASISDPAIR_ONLY.S | 15 ++ .../tests/AArch64/SIMD/ADDV_ASIMDALL_ONLY.S | 45 ++++ .../tests/AArch64/SIMD/ADD_ASIMDSAME_ONLY.S | 70 ++++++ .../tests/AArch64/SIMD/AND_ASIMDSAME_ONLY.S | 33 +++ .../tests/AArch64/SIMD/BIC_ASIMDIMM_L.S | 67 ++++++ .../tests/AArch64/SIMD/BIC_ASIMDSAME_ONLY.S | 20 ++ .../tests/AArch64/SIMD/BIF_ASIMDSAME_ONLY.S | 20 ++ .../tests/AArch64/SIMD/BIT_ASIMDSAME_ONLY.S | 20 ++ .../tests/AArch64/SIMD/BSL_ASIMDSAME_ONLY.S | 20 ++ .../tests/AArch64/SIMD/CMGE_ASISDMISC_Z.S | 14 ++ .../tests/AArch64/SIMD/CMHS_ASIMDSAME_ONLY.S | 118 ++++++++++ .../tests/AArch64/SIMD/CMLE_ASIMDMISC_Z.S | 111 +++++++++ .../tests/AArch64/SIMD/CMLT_ASIMDMISC_Z.S | 111 +++++++++ .../tests/AArch64/SIMD/CMTST_ASIMDSAME_ONLY.S | 118 ++++++++++ .../tests/AArch64/SIMD/CMcc_ASIMDMISC_Z.S | 189 ++++++++++++++++ .../tests/AArch64/SIMD/CMcc_ASIMDSAME_ONLY.S | 210 ++++++++++++++++++ .../tests/AArch64/SIMD/CNT_ASIMDMISC_R.S | 17 ++ .../tests/AArch64/SIMD/DUP_ASIMDINS_DV_V.S | 104 +++++++++ .../tests/AArch64/SIMD/DUP_ASISDONE_ONLY.S | 59 +++++ .../tests/AArch64/SIMD/EOR_ASIMDSAME_ONLY.S | 20 ++ .../tests/AArch64/SIMD/EXT_ASIMDINS_ONLY.S | 20 ++ .../tests/AArch64/SIMD/FADD_ASIMDSAME_ONLY.S | 71 ++++++ .../tests/AArch64/SIMD/FCVTZU_ASISDMISC_R.S | 41 ++++ .../tests/AArch64/SIMD/FDIV_ASIMDSAME_ONLY.S | 57 +++++ .../AArch64/SIMD/FMAXV_ASIMDALL_ONLY_SD_4S.S | 9 + .../AArch64/SIMD/FMINV_ASIMDALL_ONLY_SD_4S.S | 9 + .../tests/AArch64/SIMD/FMLA_ASIMDELEM_R_SD.S | 80 +++++++ .../tests/AArch64/SIMD/FMLA_ASIMDSAME_ONLY.S | 80 +++++++ .../remill/tests/AArch64/SIMD/FMOV_VECTORS.S | 18 ++ .../tests/AArch64/SIMD/FMUL_ASIMDELEM_R_SD.S | 85 +++++++ .../tests/AArch64/SIMD/FMUL_ASIMDSAME_ONLY.S | 71 ++++++ .../tests/AArch64/SIMD/FRINTM_ASIMDMISC_R.S | 62 ++++++ .../tests/AArch64/SIMD/FSUB_ASIMDSAME_ONLY.S | 57 +++++ .../tests/AArch64/SIMD/INS_ASIMDINS_IV_V.S | 63 ++++++ .../tests/AArch64/SIMD/NOT_ASIMDMISC_R.S | 18 ++ .../tests/AArch64/SIMD/ORR_ASIMDSAME_ONLY.S | 20 ++ .../tests/AArch64/SIMD/REV32_ASIMDMISC_R.S | 63 ++++++ .../tests/AArch64/SIMD/SADDW_ASIMDDIFF_W.S | 95 ++++++++ .../tests/AArch64/SIMD/SCVTF_ASIMDMISC_R.S | 98 ++++++++ .../tests/AArch64/SIMD/SHLL_ASIMDMISC_S.S | 89 ++++++++ .../tests/AArch64/SIMD/SHL_ASIMDSHF_R.S | 110 +++++++++ .../tests/AArch64/SIMD/SMAXP_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/SMAXV_ASIMDALL_ONLY.S | 45 ++++ .../tests/AArch64/SIMD/SMAX_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/SMINP_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/SMINV_ASIMDALL_ONLY.S | 45 ++++ .../tests/AArch64/SIMD/SMIN_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/SSHLL_ASIMDSHF_L.S | 89 ++++++++ .../tests/AArch64/SIMD/SSHL_ASIMDSAME_ONLY.S | 119 ++++++++++ .../tests/AArch64/SIMD/SSHR_ASIMDSHF_R.S | 186 ++++++++++++++++ .../tests/AArch64/SIMD/SUB_ASIMDSAME_ONLY.S | 70 ++++++ .../remill/tests/AArch64/SIMD/TBL_ASIMDTBL.S | 67 ++++++ .../tests/AArch64/SIMD/UADDL_ASIMDDIFF_L.S | 95 ++++++++ .../tests/AArch64/SIMD/UADDW_ASIMDDIFF_W.S | 95 ++++++++ .../tests/AArch64/SIMD/UCVTF_ASIMDMISC_R.S | 98 ++++++++ .../tests/AArch64/SIMD/UMAXP_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/UMAXV_ASIMDALL_ONLY.S | 45 ++++ .../tests/AArch64/SIMD/UMAX_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/UMINP_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/UMINV_ASIMDALL_ONLY.S | 45 ++++ .../tests/AArch64/SIMD/UMIN_ASIMDSAME_ONLY.S | 60 +++++ .../tests/AArch64/SIMD/USHLL_ASIMDSHF_L.S | 89 ++++++++ .../tests/AArch64/SIMD/USHL_ASIMDSAME_ONLY.S | 119 ++++++++++ .../tests/AArch64/SIMD/USHL_ASISDSAME_ONLY.S | 37 +++ .../tests/AArch64/SIMD/USHR_ASIMDSHF_R.S | 167 ++++++++++++++ .../tests/AArch64/SIMD/USHR_ASISDSHF_R.S | 9 + .../tests/AArch64/SIMD/XTN_ASIMDMISC_N.S | 89 ++++++++ backend/remill/tests/AArch64/Tests.S | 70 +++++- 141 files changed, 8207 insertions(+), 306 deletions(-) create mode 100644 backend/remill/tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S create mode 100644 backend/remill/tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S create mode 100644 backend/remill/tests/AArch64/BINARY/FMAX_t_FLOATDP2.S create mode 100644 backend/remill/tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S create mode 100644 backend/remill/tests/AArch64/BINARY/FNMSUB_t_FLOATDP3.S create mode 100644 backend/remill/tests/AArch64/BINARY/FSQRT_t_FLOATDP1.S create mode 100644 backend/remill/tests/AArch64/BINARY/UMSUBL_64WA_DP_3SRC.S create mode 100644 backend/remill/tests/AArch64/BITBYTE/CLS_n_DP_1SRC.S create mode 100644 backend/remill/tests/AArch64/CONVERT/FCVTAS_nS_FLOAT2INT.S create mode 100644 backend/remill/tests/AArch64/CONVERT/FCVTZS_64S_FLOAT2INT.S create mode 100644 backend/remill/tests/AArch64/CONVERT/FRINTA_t_FLOATDP1.S create mode 100644 backend/remill/tests/AArch64/CONVERT/FRINTM_t_FLOATDP1.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/LD1R_ASISDLSO_R1.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSOP_SINGLE.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSO_SINGLE.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/LDUR_FP_LDST_UNSCALED.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/MOVN_n_MOVEWIDE.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSOP_SINGLE.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSO_SINGLE.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/STP_FP_LDSTPAIR.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/STR_FP_LDST.S create mode 100644 backend/remill/tests/AArch64/DATAXFER/STUR_FP_LDST_UNSCALED.S create mode 100644 backend/remill/tests/AArch64/LOGICAL/ASRV_n_DP_2SRC.S create mode 100644 backend/remill/tests/AArch64/LOGICAL/LSLV_n_DP_2SRC.S create mode 100644 backend/remill/tests/AArch64/LOGICAL/LSRV_n_DP_2SRC.S create mode 100644 backend/remill/tests/AArch64/LOGICAL/RORV_n_DP_2SRC.S create mode 100644 backend/remill/tests/AArch64/SIMD/ADDP_ASISDPAIR_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/AND_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/BIC_ASIMDIMM_L.S create mode 100644 backend/remill/tests/AArch64/SIMD/CMGE_ASISDMISC_Z.S create mode 100644 backend/remill/tests/AArch64/SIMD/CMHS_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/CMLE_ASIMDMISC_Z.S create mode 100644 backend/remill/tests/AArch64/SIMD/CMLT_ASIMDMISC_Z.S create mode 100644 backend/remill/tests/AArch64/SIMD/CMTST_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/CNT_ASIMDMISC_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/DUP_ASIMDINS_DV_V.S create mode 100644 backend/remill/tests/AArch64/SIMD/DUP_ASISDONE_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/FADD_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/FCVTZU_ASISDMISC_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/FDIV_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/FMLA_ASIMDELEM_R_SD.S create mode 100644 backend/remill/tests/AArch64/SIMD/FMLA_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/FMUL_ASIMDELEM_R_SD.S create mode 100644 backend/remill/tests/AArch64/SIMD/FMUL_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/FRINTM_ASIMDMISC_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/FSUB_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/INS_ASIMDINS_IV_V.S create mode 100644 backend/remill/tests/AArch64/SIMD/REV32_ASIMDMISC_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/SADDW_ASIMDDIFF_W.S create mode 100644 backend/remill/tests/AArch64/SIMD/SCVTF_ASIMDMISC_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/SHLL_ASIMDMISC_S.S create mode 100644 backend/remill/tests/AArch64/SIMD/SHL_ASIMDSHF_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/SSHLL_ASIMDSHF_L.S create mode 100644 backend/remill/tests/AArch64/SIMD/SSHL_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/SSHR_ASIMDSHF_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/TBL_ASIMDTBL.S create mode 100644 backend/remill/tests/AArch64/SIMD/UADDL_ASIMDDIFF_L.S create mode 100644 backend/remill/tests/AArch64/SIMD/UADDW_ASIMDDIFF_W.S create mode 100644 backend/remill/tests/AArch64/SIMD/UCVTF_ASIMDMISC_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/USHLL_ASIMDSHF_L.S create mode 100644 backend/remill/tests/AArch64/SIMD/USHL_ASIMDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/USHL_ASISDSAME_ONLY.S create mode 100644 backend/remill/tests/AArch64/SIMD/USHR_ASIMDSHF_R.S create mode 100644 backend/remill/tests/AArch64/SIMD/XTN_ASIMDMISC_N.S diff --git a/.gitignore b/.gitignore index 5b32c21c..26f9f91b 100644 --- a/.gitignore +++ b/.gitignore @@ -130,4 +130,8 @@ SHA* elfconv-v* !browser/* -!release/outdir/index.html \ No newline at end of file +!release/outdir/index.html + +# AI +SKILLS.md +skills \ No newline at end of file diff --git a/backend/remill/lib/Arch/AArch64/Arch.cpp b/backend/remill/lib/Arch/AArch64/Arch.cpp index ee687324..2e9556fc 100644 --- a/backend/remill/lib/Arch/AArch64/Arch.cpp +++ b/backend/remill/lib/Arch/AArch64/Arch.cpp @@ -3542,7 +3542,7 @@ bool TryDecodeFCVTZS_32S_FLOAT2INT(const InstData &data, Instruction &inst) { // FCVTZS , bool TryDecodeFCVTZS_64S_FLOAT2INT(const InstData &data, Instruction &inst) { - inst.sema_func_arg_type = SemaFuncArgType::Nothing; + inst.sema_func_arg_type = SemaFuncArgType::State; if (IsUnallocatedFloatEncoding(data)) { return false; } @@ -4610,6 +4610,22 @@ bool TryDecodeCLZ_64_DP_1SRC(const InstData &data, Instruction &inst) { return true; } +// CLS , +bool TryDecodeCLS_32_DP_1SRC(const InstData &data, Instruction &inst) { + inst.sema_func_arg_type = SemaFuncArgType::Nothing; + AddRegOperand(inst, kActionWrite, kRegW, kUseAsValue, data.Rd); + AddRegOperand(inst, kActionRead, kRegW, kUseAsValue, data.Rn); + return true; +} + +// CLS , +bool TryDecodeCLS_64_DP_1SRC(const InstData &data, Instruction &inst) { + inst.sema_func_arg_type = SemaFuncArgType::Nothing; + AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rd); + AddRegOperand(inst, kActionRead, kRegX, kUseAsValue, data.Rn); + return true; +} + static bool DecodeConditionalRegSelect(const InstData &data, Instruction &inst, RegClass r_class, int n_regs, bool invert_cond = false) { CHECK(1 <= n_regs && n_regs <= 3); diff --git a/backend/remill/lib/Arch/AArch64/Decode.cpp b/backend/remill/lib/Arch/AArch64/Decode.cpp index 6d54e8b3..bdaef9d3 100644 --- a/backend/remill/lib/Arch/AArch64/Decode.cpp +++ b/backend/remill/lib/Arch/AArch64/Decode.cpp @@ -5845,9 +5845,7 @@ bool TryDecodeSRSHR_ASIMDSHF_R(const InstData &, Instruction &) { // 30 1 // 31 0 sf 0 // CLS , -bool TryDecodeCLS_32_DP_1SRC(const InstData &, Instruction &) { - return false; -} +// Implemented in Arch.cpp // CLS CLS_64_dp_1src: // 0 x Rd 0 @@ -5883,9 +5881,7 @@ bool TryDecodeCLS_32_DP_1SRC(const InstData &, Instruction &) { // 30 1 // 31 1 sf 0 // CLS , -bool TryDecodeCLS_64_DP_1SRC(const InstData &, Instruction &) { - return false; -} +// Implemented in Arch.cpp // SEV SEV_HI_system: // 0 1 Rt 0 diff --git a/backend/remill/lib/Arch/AArch64/Semantics/BITBYTE.cpp b/backend/remill/lib/Arch/AArch64/Semantics/BITBYTE.cpp index 958c1bd4..1c754b3b 100644 --- a/backend/remill/lib/Arch/AArch64/Semantics/BITBYTE.cpp +++ b/backend/remill/lib/Arch/AArch64/Semantics/BITBYTE.cpp @@ -123,6 +123,29 @@ DEF_ISEL(CLZ_64_DP_1SRC) = CLZ; // CLZ , namespace { +// CLS , +DEF_SEM_U32(CLS_32, R32 src) { + uint32_t val = Read(src); + // CLS counts leading sign bits (same as MSB, excluding MSB itself). + // CLS(x) = CLZ(x ^ (x ASR 1)) - 1 + uint32_t xored = val ^ static_cast(static_cast(val) >> 1); + return CountLeadingZeros(xored) - uint32_t(1); +} + +// CLS , +DEF_SEM_U64(CLS_64, R64 src) { + uint64_t val = Read(src); + uint64_t xored = val ^ static_cast(static_cast(val) >> 1); + return CountLeadingZeros(xored) - uint64_t(1); +} + +} // namespace + +DEF_ISEL(CLS_32_DP_1SRC) = CLS_32; // CLS , +DEF_ISEL(CLS_64_DP_1SRC) = CLS_64; // CLS , + +namespace { + // REV16 , DEF_SEM_U32(REV16_32, R32 src) { uint32_t src_num = Read(src); diff --git a/backend/remill/lib/Arch/AArch64/Semantics/SIMD.cpp b/backend/remill/lib/Arch/AArch64/Semantics/SIMD.cpp index 4e59a4ac..cda7a56b 100644 --- a/backend/remill/lib/Arch/AArch64/Semantics/SIMD.cpp +++ b/backend/remill/lib/Arch/AArch64/Semantics/SIMD.cpp @@ -198,7 +198,7 @@ ALWAYS_INLINE static T UMax(T lhs, T rhs) { auto vec2 = prefix##ReadVI##size(src2); \ V sum = {}; \ _Pragma("unroll") for (size_t i = 0, max_i = GetVectorElemsNum(sum); i < max_i; ++i) { \ - sum[i] = prefix##binop(prefix##ExtractVI##size(vec1, i), prefix##ExtractVI##size(vec2, i)); \ + sum[i] = prefix##binop(vec1[i], vec2[i]); \ } \ return sum; \ } @@ -1606,7 +1606,7 @@ namespace { auto srcm_v = UReadVI##s_esize(srcm); \ D res{}; \ _Pragma("unroll") for (size_t i = 0; i < GetVectorElemsNum(srcn_v); i++) { \ - res[i] = uint##d_esize##_t(srcn_v[i] + srcm_v[i]); \ + res[i] = uint##d_esize##_t(srcn_v[i]) + uint##d_esize##_t(srcm_v[i]); \ } \ return res; \ } \ @@ -1617,7 +1617,7 @@ namespace { D res{}; \ auto res_len = GetVectorElemsNum(res); \ _Pragma("unroll") for (size_t i = res_len; i < GetVectorElemsNum(srcn_v); i++) { \ - res[i - res_len] = uint##d_esize##_t(srcn_v[i] + srcm_v[i]); \ + res[i - res_len] = uint##d_esize##_t(srcn_v[i]) + uint##d_esize##_t(srcm_v[i]); \ } \ return res; \ } diff --git a/backend/remill/tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S b/backend/remill/tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S new file mode 100644 index 00000000..f0c8ed71 --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S @@ -0,0 +1,35 @@ +/* ADC , , */ +TEST_BEGIN(ADC_32_ADDSUB_CARRY, adc_w9_w0_w1, 2) +TEST_INPUTS( + 0, 0, + 0, 1, + 1, 0, + 1, 1, + 0xFFFFFFFF, 0xFFFFFFFF, + 0, 0xFFFFFFFF, + 0xfafbfbfd, 0xf1f2f3f4, + 0x0a0b0c0d, 0x01020304) + + adc w9, ARG1_32, ARG2_32 +TEST_END + + +/* ADC , , */ +TEST_BEGIN(ADC_64_ADDSUB_CARRY, adc_x9_x0_x1, 2) +TEST_INPUTS( + 0, 0, + 0, 1, + 1, 0, + 1, 1, + 0xFFFFFFFF, 0xFFFFFFFF, + 0, 0xFFFFFFFF, + 0xfafbfbfd, 0xf1f2f3f4, + 0x0a0b0c0d, 0x01020304, + 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFF00000000, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF00000000, + 0xFFFFFFFFFFFFFFFF, 0, + 0, 0xFFFFFFFFFFFFFFFF) + + adc x9, ARG1_64, ARG2_64 +TEST_END diff --git a/backend/remill/tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S b/backend/remill/tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S new file mode 100644 index 00000000..617f487d --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S @@ -0,0 +1,13 @@ +TEST_BEGIN(FCMPE_DZ_FLOATCMP, fcmpe_d0_0, 1) +TEST_INPUTS( + 0x0000000000000000, /* +0.0 */ + 0x8000000000000000, /* -0.0 */ + 0x3ff0000000000000, /* 1.0 */ + 0xbff0000000000000, /* -1.0 */ + 0x7ff0000000000000, /* +inf */ + 0xfff0000000000000, /* -inf */ + 0x7ff8000000000000) /* NaN */ + + fmov d0, ARG1_64 + fcmpe d0, #0.0 +TEST_END diff --git a/backend/remill/tests/AArch64/BINARY/FMADD_t_FLOATDP3.S b/backend/remill/tests/AArch64/BINARY/FMADD_t_FLOATDP3.S index a15968bc..401ccea8 100644 --- a/backend/remill/tests/AArch64/BINARY/FMADD_t_FLOATDP3.S +++ b/backend/remill/tests/AArch64/BINARY/FMADD_t_FLOATDP3.S @@ -1,7 +1,7 @@ /* * Copyright (c) 2017 Trail of Bits, Inc. * - * Licensed under the Apache License, Version 2.0 (the "License")// + * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * @@ -19,10 +19,10 @@ TEST_BEGIN(FMADD_S_FLOATDP3, fmadd_s_pos_floatdp3, 2) TEST_INPUTS( 0x00000000, 0x00000000, 0x00000000, 0x00000001, - // 0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffff, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffff, 0x40000000, // WILL FAIL (Native no underflow, lifted says yes) - // 0x40000000, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes) + 0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes) + 0x3fffffff, 0x3fffffff, + 0x3fffffff, 0x40000000, + 0x40000000, 0x3fffffff, 0x7FFFFFFF, 0x7FFFFFFF, 0x80000000, 0x7FFFFFFF, 0x7FFFFFFF, 0x80000000, @@ -39,10 +39,10 @@ TEST_BEGIN(FMADD_S_FLOATDP3, fmadd_s_neg_floatdp3, 2) TEST_INPUTS( 0x00000000, 0x00000000, 0x00000000, 0x00000001, - // 0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffff, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffff, 0x40000000, // WILL FAIL (Native no underflow, lifted says yes) - // 0x40000000, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes) + 0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes) + 0x3fffffff, 0x3fffffff, + 0x3fffffff, 0x40000000, + 0x40000000, 0x3fffffff, 0x7FFFFFFF, 0x7FFFFFFF, 0x80000000, 0x7FFFFFFF, 0x7FFFFFFF, 0x80000000, @@ -60,10 +60,10 @@ TEST_BEGIN(FMADD_D_FLOATDP3, fmadd_d_pos_floatdp3, 2) TEST_INPUTS( 0x0000000000000000, 0x0000000000000000, // 0, 0 0x0000000000000000, 0x0000000000000001, // 0, smallest representable float - // 0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0 // WILL FAIL (Native no underflow, lifted says yes) - // 0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999 // WILL FAIL (Native no underflow, lifted says yes) + 0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float + 0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both + 0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0 + 0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999 0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF, // NaN, NaN 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, // -0.0, NaN 0x7FFFFFFFFFFFFFFF, 0x8000000000000000, // NaN, -0.0 @@ -80,10 +80,10 @@ TEST_BEGIN(FMADD_D_FLOATDP3, fmadd_d_neg_floatdp3, 2) TEST_INPUTS( 0x0000000000000000, 0x0000000000000000, // 0, 0 0x0000000000000000, 0x0000000000000001, // 0, smallest representable float - // 0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both // WILL FAIL (Native no underflow, lifted says yes) - // 0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0 // WILL FAIL (Native no underflow, lifted says yes) - // 0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999 // WILL FAIL (Native no underflow, lifted says yes) + 0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float + 0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both + 0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0 + 0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999 0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF, // NaN, NaN 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, // -0.0, NaN 0x7FFFFFFFFFFFFFFF, 0x8000000000000000, // NaN, -0.0 diff --git a/backend/remill/tests/AArch64/BINARY/FMAX_t_FLOATDP2.S b/backend/remill/tests/AArch64/BINARY/FMAX_t_FLOATDP2.S new file mode 100644 index 00000000..5f7f9034 --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/FMAX_t_FLOATDP2.S @@ -0,0 +1,129 @@ +TEST_BEGIN(FMAX_S_FLOATDP2, fmax_s4_s0_s1, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0xff800000, /* inf, -inf */ + 0x7fc00000, 0x3f800000, /* nan, 1.0 */ + 0xbf800000, 0xc0000000) /* -1.0, -2.0 */ + + fmov s0, ARG1_32 + fmov s1, ARG2_32 + fmax s4, s0, s1 +TEST_END + +TEST_BEGIN(FMAX_S_FLOATDP2_NEG, fmax_s4_s0_s1_neg, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0xff800000, /* inf, -inf */ + 0x7fc00000, 0x3f800000, /* nan, 1.0 */ + 0xbf800000, 0xc0000000) /* -1.0, -2.0 */ + + fmov s0, ARG1_32 + fmov s1, ARG2_32 + fmax s4, s0, s1 +TEST_END + +TEST_BEGIN(FMAX_S_FLOATDP2_ZERO, fmax_s4_s0_s1_zero, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0xff800000, /* inf, -inf */ + 0x7fc00000, 0x3f800000, /* nan, 1.0 */ + 0xbf800000, 0xc0000000) /* -1.0, -2.0 */ + + fmov s0, ARG1_32 + fmov s1, ARG2_32 + fmax s4, s0, s1 +TEST_END + +TEST_BEGIN(FMAX_S_FLOATDP2_SAME, fmax_s4_s0_s1_same, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0xff800000, /* inf, -inf */ + 0x7fc00000, 0x3f800000, /* nan, 1.0 */ + 0xbf800000, 0xc0000000) /* -1.0, -2.0 */ + + fmov s0, ARG1_32 + fmov s1, ARG2_32 + fmax s4, s0, s1 +TEST_END + +TEST_BEGIN(FMAX_S_FLOATDP2_LARGE, fmax_s4_s0_s1_large, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0xff800000, /* inf, -inf */ + 0x7fc00000, 0x3f800000, /* nan, 1.0 */ + 0xbf800000, 0xc0000000) /* -1.0, -2.0 */ + + fmov s0, ARG1_32 + fmov s1, ARG2_32 + fmax s4, s0, s1 +TEST_END + +TEST_BEGIN(FMAX_D_FLOATDP2, fmax_d4_d0_d1, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x0000000000000000, 0x3FF0000000000000, /* 0.0, 1.0 */ + 0x7FF0000000000000, 0xFFF0000000000000, /* inf, -inf */ + 0x7FF8000000000000, 0x3FF0000000000000, /* nan, 1.0 */ + 0xBFF0000000000000, 0xC000000000000000) /* -1.0, -2.0 */ + + fmov d0, ARG1_64 + fmov d1, ARG2_64 + fmax d4, d0, d1 +TEST_END + +TEST_BEGIN(FMAX_D_FLOATDP2_NEG, fmax_d4_d0_d1_neg, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x0000000000000000, 0x3FF0000000000000, /* 0.0, 1.0 */ + 0x7FF0000000000000, 0xFFF0000000000000, /* inf, -inf */ + 0x7FF8000000000000, 0x3FF0000000000000, /* nan, 1.0 */ + 0xBFF0000000000000, 0xC000000000000000) /* -1.0, -2.0 */ + + fmov d0, ARG1_64 + fmov d1, ARG2_64 + fmax d4, d0, d1 +TEST_END + +TEST_BEGIN(FMAX_D_FLOATDP2_ZERO, fmax_d4_d0_d1_zero, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x0000000000000000, 0x3FF0000000000000, /* 0.0, 1.0 */ + 0x7FF0000000000000, 0xFFF0000000000000, /* inf, -inf */ + 0x7FF8000000000000, 0x3FF0000000000000, /* nan, 1.0 */ + 0xBFF0000000000000, 0xC000000000000000) /* -1.0, -2.0 */ + + fmov d0, ARG1_64 + fmov d1, ARG2_64 + fmax d4, d0, d1 +TEST_END + +TEST_BEGIN(FMAX_D_FLOATDP2_SAME, fmax_d4_d0_d1_same, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x0000000000000000, 0x3FF0000000000000, /* 0.0, 1.0 */ + 0x7FF0000000000000, 0xFFF0000000000000, /* inf, -inf */ + 0x7FF8000000000000, 0x3FF0000000000000, /* nan, 1.0 */ + 0xBFF0000000000000, 0xC000000000000000) /* -1.0, -2.0 */ + + fmov d0, ARG1_64 + fmov d1, ARG2_64 + fmax d4, d0, d1 +TEST_END + +TEST_BEGIN(FMAX_D_FLOATDP2_LARGE, fmax_d4_d0_d1_large, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x0000000000000000, 0x3FF0000000000000, /* 0.0, 1.0 */ + 0x7FF0000000000000, 0xFFF0000000000000, /* inf, -inf */ + 0x7FF8000000000000, 0x3FF0000000000000, /* nan, 1.0 */ + 0xBFF0000000000000, 0xC000000000000000) /* -1.0, -2.0 */ + + fmov d0, ARG1_64 + fmov d1, ARG2_64 + fmax d4, d0, d1 +TEST_END diff --git a/backend/remill/tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S b/backend/remill/tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S new file mode 100644 index 00000000..50903578 --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S @@ -0,0 +1,25 @@ +TEST_BEGIN(FMSUB_S_FLOATDP3, fmsub_s0_s1_s2_s3, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x40400000, 0xbf800000, /* 3.0, -1.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0x3f800000, /* +inf, 1.0 */ + 0x41200000, 0x41200000) /* 10.0, 10.0 */ + + fmov s1, ARG1_32 + fmov s2, ARG2_32 + fmsub s0, s1, s2, s3 +TEST_END + +TEST_BEGIN(FMSUB_D_FLOATDP3, fmsub_d0_d1_d2_d3, 2) +TEST_INPUTS( + 0x3ff0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x4008000000000000, 0xbff0000000000000, /* 3.0, -1.0 */ + 0x0000000000000000, 0x3ff0000000000000, /* 0.0, 1.0 */ + 0x7ff0000000000000, 0x3ff0000000000000, /* +inf, 1.0 */ + 0x4024000000000000, 0x4024000000000000) /* 10.0, 10.0 */ + + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fmsub d0, d1, d2, d3 +TEST_END diff --git a/backend/remill/tests/AArch64/BINARY/FNMSUB_t_FLOATDP3.S b/backend/remill/tests/AArch64/BINARY/FNMSUB_t_FLOATDP3.S new file mode 100644 index 00000000..62d7ebc8 --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/FNMSUB_t_FLOATDP3.S @@ -0,0 +1,25 @@ +TEST_BEGIN(FNMSUB_S_FLOATDP3, fnmsub_s0_s1_s2_s3, 2) +TEST_INPUTS( + 0x3f800000, 0x40000000, /* 1.0, 2.0 */ + 0x40400000, 0xbf800000, /* 3.0, -1.0 */ + 0x00000000, 0x3f800000, /* 0.0, 1.0 */ + 0x7f800000, 0x3f800000, /* +inf, 1.0 */ + 0x41200000, 0x41200000) /* 10.0, 10.0 */ + + fmov s1, ARG1_32 + fmov s2, ARG2_32 + fnmsub s0, s1, s2, s3 +TEST_END + +TEST_BEGIN(FNMSUB_D_FLOATDP3, fnmsub_d0_d1_d2_d3, 2) +TEST_INPUTS( + 0x3ff0000000000000, 0x4000000000000000, /* 1.0, 2.0 */ + 0x4008000000000000, 0xbff0000000000000, /* 3.0, -1.0 */ + 0x0000000000000000, 0x3ff0000000000000, /* 0.0, 1.0 */ + 0x7ff0000000000000, 0x3ff0000000000000, /* +inf, 1.0 */ + 0x4024000000000000, 0x4024000000000000) /* 10.0, 10.0 */ + + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fnmsub d0, d1, d2, d3 +TEST_END diff --git a/backend/remill/tests/AArch64/BINARY/FSQRT_t_FLOATDP1.S b/backend/remill/tests/AArch64/BINARY/FSQRT_t_FLOATDP1.S new file mode 100644 index 00000000..34b3ea7f --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/FSQRT_t_FLOATDP1.S @@ -0,0 +1,25 @@ +TEST_BEGIN(FSQRT_S_FLOATDP1, fsqrt_s0_s1, 1) +TEST_INPUTS( + 0x40800000, /* 4.0 */ + 0x41c80000, /* 25.0 */ + 0x3f800000, /* 1.0 */ + 0x00000000, /* +0.0 */ + 0x80000000, /* -0.0 */ + 0x7f800000) /* +inf */ + + fmov s1, ARG1_32 + fsqrt s0, s1 +TEST_END + +TEST_BEGIN(FSQRT_D_FLOATDP1, fsqrt_d0_d1, 1) +TEST_INPUTS( + 0x4010000000000000, /* 4.0 */ + 0x4039000000000000, /* 25.0 */ + 0x3ff0000000000000, /* 1.0 */ + 0x0000000000000000, /* +0.0 */ + 0x8000000000000000, /* -0.0 */ + 0x7ff0000000000000) /* +inf */ + + fmov d1, ARG1_64 + fsqrt d0, d1 +TEST_END diff --git a/backend/remill/tests/AArch64/BINARY/UMSUBL_64WA_DP_3SRC.S b/backend/remill/tests/AArch64/BINARY/UMSUBL_64WA_DP_3SRC.S new file mode 100644 index 00000000..b6662804 --- /dev/null +++ b/backend/remill/tests/AArch64/BINARY/UMSUBL_64WA_DP_3SRC.S @@ -0,0 +1,12 @@ +/* UMSUBL , , , */ +TEST_BEGIN(UMSUBL_64WA_DP_3SRC, umsubl_x9_w0_w1_x2, 3) +TEST_INPUTS( + 0, 0, 0, + 1, 1, 0, + 1, 1, 1, + 0xFFFFFFFF, 0xFFFFFFFF, 0, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFFFFFFFFFF, + 100, 200, 50000) + + umsubl x9, ARG1_32, ARG2_32, x2 +TEST_END diff --git a/backend/remill/tests/AArch64/BITBYTE/CLS_n_DP_1SRC.S b/backend/remill/tests/AArch64/BITBYTE/CLS_n_DP_1SRC.S new file mode 100644 index 00000000..8662e79d --- /dev/null +++ b/backend/remill/tests/AArch64/BITBYTE/CLS_n_DP_1SRC.S @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2017 Trail of Bits, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* CLS , */ +TEST_BEGIN(CLS_32_DP_1SRC, cls_w1_w0, 1) +TEST_INPUTS( + 0, + 1, + 0x7FFFFFFF, + 0x80000000, + 0xFFFFFFFF, + 0xfafbfbfd, + 0xf1f2f3f4, + 0x0a0b0c0d, + 0x01020304, + 0x00000001, + 0xFFFFFFFE, + 0x0000FFFF, + 0xFFFF0000 +) + + cls w1, w0 +TEST_END + +/* CLS , */ +TEST_BEGIN(CLS_64_DP_1SRC, cls_x1_x0, 1) +TEST_INPUTS( + 0, + 1, + 0x7FFFFFFFFFFFFFFF, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF00000000, + 0xf1f2f3f4fafbfbfd, + 0x010203040a0b0c0d, + 0x0000000000000001, + 0xFFFFFFFFFFFFFFFE, + 0x00000000FFFFFFFF, + 0xFFFFFFFF00000000 +) + + cls x1, x0 +TEST_END diff --git a/backend/remill/tests/AArch64/CMakeLists.txt b/backend/remill/tests/AArch64/CMakeLists.txt index 06b59e3c..e08b6595 100644 --- a/backend/remill/tests/AArch64/CMakeLists.txt +++ b/backend/remill/tests/AArch64/CMakeLists.txt @@ -21,7 +21,6 @@ enable_language(ASM) include_directories("/usr/lib/llvm-16/include") add_executable(lift-aarch64-tests - EXCLUDE_FROM_ALL Lift.cpp Tests.S ) @@ -52,7 +51,6 @@ target_include_directories(lift-aarch64-tests PRIVATE "${CMAKE_SOURCE_DIR}/backe target_include_directories(lift-aarch64-tests PRIVATE "${CMAKE_SOURCE_DIR}") add_executable(run-aarch64-tests - EXCLUDE_FROM_ALL Run.cpp Tests.S tests_aarch64.S @@ -66,7 +64,7 @@ set_target_properties(run-aarch64-tests PROPERTIES add_custom_command( OUTPUT tests_aarch64.bc COMMAND lift-aarch64-tests --arch aarch64 --bc_out tests_aarch64.bc - DEPENDS lift-aarch64-tests semantics + DEPENDS lift-aarch64-tests "${REMILL_BUILD_SEMANTICS_DIR_AARCH64}/aarch64.bc" ) add_custom_command( @@ -103,4 +101,4 @@ target_compile_options(run-aarch64-tests message(STATUS "Adding test: aarch64 as run-aarch64-tests") add_test(NAME "aarch64" COMMAND "run-aarch64-tests") -add_dependencies(test_dependencies run-aarch64-tests) +add_dependencies(test_dependencies run-aarch64-tests aarch64) diff --git a/backend/remill/tests/AArch64/CONVERT/FCVTAS_nS_FLOAT2INT.S b/backend/remill/tests/AArch64/CONVERT/FCVTAS_nS_FLOAT2INT.S new file mode 100644 index 00000000..3126b1c7 --- /dev/null +++ b/backend/remill/tests/AArch64/CONVERT/FCVTAS_nS_FLOAT2INT.S @@ -0,0 +1,12 @@ +TEST_BEGIN(FCVTAS_64D_FLOAT2INT, fcvtas_x0_d0, 1) +TEST_INPUTS( + 0x4004000000000000, /* 2.5 -> 3 (round to nearest, ties away) */ + 0xc004000000000000, /* -2.5 -> -3 */ + 0x3ff8000000000000, /* 1.5 -> 2 */ + 0x0000000000000000, /* 0.0 -> 0 */ + 0x3ff0000000000000, /* 1.0 -> 1 */ + 0x4024000000000000) /* 10.0 -> 10 */ + + fmov d0, ARG1_64 + fcvtas x0, d0 +TEST_END diff --git a/backend/remill/tests/AArch64/CONVERT/FCVTZS_64S_FLOAT2INT.S b/backend/remill/tests/AArch64/CONVERT/FCVTZS_64S_FLOAT2INT.S new file mode 100644 index 00000000..a662bd7e --- /dev/null +++ b/backend/remill/tests/AArch64/CONVERT/FCVTZS_64S_FLOAT2INT.S @@ -0,0 +1,12 @@ +TEST_BEGIN(FCVTZS_64S_FLOAT2INT, fcvtzs_x0_s0, 1) +TEST_INPUTS( + 0x40200000, /* 2.5 -> 2 (truncate) */ + 0xc0200000, /* -2.5 -> -2 */ + 0x3fc00000, /* 1.5 -> 1 */ + 0x00000000, /* 0.0 -> 0 */ + 0x3f800000, /* 1.0 -> 1 */ + 0x41200000) /* 10.0 -> 10 */ + + fmov s0, ARG1_32 + fcvtzs x0, s0 +TEST_END diff --git a/backend/remill/tests/AArch64/CONVERT/FRINTA_t_FLOATDP1.S b/backend/remill/tests/AArch64/CONVERT/FRINTA_t_FLOATDP1.S new file mode 100644 index 00000000..c872e974 --- /dev/null +++ b/backend/remill/tests/AArch64/CONVERT/FRINTA_t_FLOATDP1.S @@ -0,0 +1,12 @@ +TEST_BEGIN(FRINTA_D_FLOATDP1, frinta_d0_d1, 1) +TEST_INPUTS( + 0x4004000000000000, /* 2.5 -> 3.0 (round away from zero) */ + 0xc004000000000000, /* -2.5 -> -3.0 */ + 0x3ff8000000000000, /* 1.5 -> 2.0 */ + 0x0000000000000000, /* 0.0 -> 0.0 */ + 0x400c000000000000, /* 3.5 -> 4.0 */ + 0x4024000000000000) /* 10.0 -> 10.0 */ + + fmov d1, ARG1_64 + frinta d0, d1 +TEST_END diff --git a/backend/remill/tests/AArch64/CONVERT/FRINTM_t_FLOATDP1.S b/backend/remill/tests/AArch64/CONVERT/FRINTM_t_FLOATDP1.S new file mode 100644 index 00000000..33ed49eb --- /dev/null +++ b/backend/remill/tests/AArch64/CONVERT/FRINTM_t_FLOATDP1.S @@ -0,0 +1,25 @@ +TEST_BEGIN(FRINTM_D_FLOATDP1, frintm_d0_d1, 1) +TEST_INPUTS( + 0x4004000000000000, /* 2.5 -> 2.0 (floor) */ + 0xc004000000000000, /* -2.5 -> -3.0 */ + 0x3ff8000000000000, /* 1.5 -> 1.0 */ + 0x0000000000000000, /* 0.0 -> 0.0 */ + 0x400c000000000000, /* 3.5 -> 3.0 */ + 0xbff0000000000000) /* -1.0 -> -1.0 */ + + fmov d1, ARG1_64 + frintm d0, d1 +TEST_END + +TEST_BEGIN(FRINTM_S_FLOATDP1, frintm_s0_s1, 1) +TEST_INPUTS( + 0x40200000, /* 2.5 -> 2.0 */ + 0xc0200000, /* -2.5 -> -3.0 */ + 0x3fc00000, /* 1.5 -> 1.0 */ + 0x00000000, /* 0.0 -> 0.0 */ + 0x40600000, /* 3.5 -> 3.0 */ + 0xbf800000) /* -1.0 -> -1.0 */ + + fmov s1, ARG1_32 + frintm s0, s1 +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/FMOV_NToN.S b/backend/remill/tests/AArch64/DATAXFER/FMOV_NToN.S index 3227e834..9c7f9616 100644 --- a/backend/remill/tests/AArch64/DATAXFER/FMOV_NToN.S +++ b/backend/remill/tests/AArch64/DATAXFER/FMOV_NToN.S @@ -17,7 +17,17 @@ TEST_BEGIN(FMOV_32S_FLOAT2INT, fmov_f32_to_i32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x3ff0000000000000, /* 1.0 */ + 0x4000000000000000, /* 2.0 */ + 0x0000000000000000, /* 0.0 */ + 0xbff0000000000000, /* -1.0 */ + 0x7ff0000000000000, /* +inf */ + 0x7ff8000000000000, /* nan */ + 0xC1F7FFFFFFD00000, + 0x41F7FFFFFFD00000) + + fmov d0, ARG1_64 fmov w0, s0 fmov w1, s0 fmov w3, s2 @@ -42,7 +52,17 @@ TEST_INPUTS( TEST_END TEST_BEGIN(FMOV_64D_FLOAT2INT, fmov_f64_to_i64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x3ff0000000000000, /* 1.0 */ + 0x4000000000000000, /* 2.0 */ + 0x0000000000000000, /* 0.0 */ + 0xbff0000000000000, /* -1.0 */ + 0x7ff0000000000000, /* +inf */ + 0x7ff8000000000000, /* nan */ + 0xC1F7FFFFFFD00000, + 0x41F7FFFFFFD00000) + + fmov d0, ARG1_64 fmov x0, d0 fmov x1, d0 fmov x3, d2 @@ -65,7 +85,17 @@ TEST_INPUTS( TEST_END TEST_BEGIN(FMOV_S_FLOATDP1, fmov_s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x3ff0000000000000, /* 1.0 */ + 0x4000000000000000, /* 2.0 */ + 0x0000000000000000, /* 0.0 */ + 0xbff0000000000000, /* -1.0 */ + 0x7ff0000000000000, /* +inf */ + 0x7ff8000000000000, /* nan */ + 0xC1F7FFFFFFD00000, + 0x41F7FFFFFFD00000) + + fmov d0, ARG1_64 fmov s1, s0 fmov s3, s2 fmov s5, s4 @@ -73,7 +103,17 @@ TEST_INPUTS(0) TEST_END TEST_BEGIN(FMOV_D_FLOATDP1, fmov_d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x3ff0000000000000, /* 1.0 */ + 0x4000000000000000, /* 2.0 */ + 0x0000000000000000, /* 0.0 */ + 0xbff0000000000000, /* -1.0 */ + 0x7ff0000000000000, /* +inf */ + 0x7ff8000000000000, /* nan */ + 0xC1F7FFFFFFD00000, + 0x41F7FFFFFFD00000) + + fmov d0, ARG1_64 fmov d1, d0 fmov d3, d2 fmov d5, d4 diff --git a/backend/remill/tests/AArch64/DATAXFER/INS_ASIMDINS_IR_R.S b/backend/remill/tests/AArch64/DATAXFER/INS_ASIMDINS_IR_R.S index b59c55c9..576aea7c 100644 --- a/backend/remill/tests/AArch64/DATAXFER/INS_ASIMDINS_IR_R.S +++ b/backend/remill/tests/AArch64/DATAXFER/INS_ASIMDINS_IR_R.S @@ -16,25 +16,57 @@ /* INS .[], */ TEST_BEGIN(INS_ASIMDINS_IR_R_B, ins_ir_r_b, 1) -TEST_INPUTS(0) - mov w3, #255 - ins v1.b[3], w3 +TEST_INPUTS( + 0, + 1, + 0x7f, + 0x80, + 0xff, + 0xdeadbeef, + 0xFFFFFFFF, + 0x41F7FFFFFFD00000) + + ins v1.b[3], ARG1_32 TEST_END TEST_BEGIN(INS_ASIMDINS_IR_R_H, ins_ir_r_h, 1) -TEST_INPUTS(0) - mov w3, #255 - ins v1.h[3], w3 +TEST_INPUTS( + 0, + 1, + 0x7fff, + 0x8000, + 0xffff, + 0xdeadbeef, + 0xFFFFFFFF, + 0x41F7FFFFFFD00000) + + ins v1.h[3], ARG1_32 TEST_END TEST_BEGIN(INS_ASIMDINS_IR_R_S, ins_ir_r_s, 1) -TEST_INPUTS(0) - mov w3, #255 - ins v1.s[3], w3 +TEST_INPUTS( + 0, + 1, + 0x7fffffff, + 0x80000000, + 0xffffffff, + 0xdeadbeef, + 0x3f800000, + 0x41F7FFFFFFD00000) + + ins v1.s[3], ARG1_32 TEST_END TEST_BEGIN(INS_ASIMDINS_IR_R_D, ins_ir_r_d, 1) -TEST_INPUTS(0) - mov x3, #255 - ins v1.d[1], x3 +TEST_INPUTS( + 0, + 1, + 0x7fffffffffffffff, + 0x8000000000000000, + 0xffffffffffffffff, + 0xdeadbeefdeadbeef, + 0x3ff0000000000000, + 0x41F7FFFFFFD00000) + + ins v1.d[1], ARG1_64 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1R_ASISDLSO_R1.S b/backend/remill/tests/AArch64/DATAXFER/LD1R_ASISDLSO_R1.S new file mode 100644 index 00000000..b39e01b3 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/LD1R_ASISDLSO_R1.S @@ -0,0 +1,103 @@ +/* LD1R {.8B}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_8B, ld1r_v0_8b, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.8b}, [x3] +TEST_END + +/* LD1R {.16B}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_16B, ld1r_v0_16b, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.16b}, [x3] +TEST_END + +/* LD1R {.4H}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_4H, ld1r_v0_4h, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.4h}, [x3] +TEST_END + +/* LD1R {.8H}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_8H, ld1r_v0_8h, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.8h}, [x3] +TEST_END + +/* LD1R {.2S}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_2S, ld1r_v0_2s, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.2s}, [x3] +TEST_END + +/* LD1R {.4S}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_4S, ld1r_v0_4s, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.4s}, [x3] +TEST_END + +/* LD1R {.1D}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_1D, ld1r_v0_1d, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.1d}, [x3] +TEST_END + +/* LD1R {.2D}, [] */ +TEST_BEGIN(LD1R_ASISDLSO_R1_2D, ld1r_v0_2d, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1r {v0.2d}, [x3] +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I1_I1.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I1_I1.S index f2050fd9..8c4ff743 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I1_I1.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I1_I1.S @@ -15,49 +15,97 @@ */ TEST_BEGIN(LD1_ASISDLSEP_I1_I1_16B, ld1_i1_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v0.16b}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_8B, ld1_i1_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.8b}, [x3], #0x8 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_8H, ld1_i1_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v1.8h}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_4H, ld1_i1_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.4h}, [x3], #0x8 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_4S, ld1_i1_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v0.4s}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_2S, ld1_i1_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.2s}, [x3], #0x8 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_2D, ld1_i1_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v0.2d}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I1_I1_1D, ld1_i1_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.1d}, [x3], #0x8 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I2_I2.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I2_I2.S index 0bf721d0..c4d8c4e8 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I2_I2.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I2_I2.S @@ -15,57 +15,129 @@ */ TEST_BEGIN(LD1_ASISDLSEP_I2_I2_16B, ld1_i2_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v3.16b, v4.16b}, [x3], #0x20 ld1 {v31.16b, v0.16b}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_8B, ld1_i2_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v3.8b, v4.8b}, [x3], #0x10 ld1 {v31.8b, v0.8b}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_8H, ld1_i2_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v3.8h, v4.8h}, [x3], #0x20 ld1 {v31.8h, v0.8h}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_4H, ld1_i2_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v3.4h, v4.4h}, [x3], #0x10 ld1 {v31.4h, v0.4h}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_4S, ld1_i2_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v3.4s, v4.4s}, [x3], #0x20 ld1 {v31.4s, v0.4s}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_2S, ld1_i2_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v3.2s, v4.2s}, [x3], #0x10 ld1 {v31.2s, v0.2s}, [x3], #0x10 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_2D, ld1_i2_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v3.2d, v4.2d}, [x3], #0x20 ld1 {v31.2d, v0.2d}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I2_I2_1D, ld1_i2_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v3.1d, v4.1d}, [x3], #0x10 ld1 {v31.1d, v0.1d}, [x3], #0x10 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I3_I3.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I3_I3.S index 1ff71fa5..3b0b1caf 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I3_I3.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I3_I3.S @@ -15,49 +15,113 @@ */ TEST_BEGIN(LD1_ASISDLSEP_I3_I3_16B, ld1_i3_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.16b, v0.16b, v1.16b}, [x3], #0x30 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_8B, ld1_i3_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.8b, v0.8b, v1.8b}, [x3], #0x18 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_8H, ld1_i3_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.8h, v0.8h, v1.8h}, [x3], #0x30 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_4H, ld1_i3_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.4h, v0.4h, v1.4h}, [x3], #0x18 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_4S, ld1_i3_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.4s, v0.4s, v1.4s}, [x3], #0x30 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_2S, ld1_i3_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.2s, v0.2s, v1.2s}, [x3], #0x18 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_2D, ld1_i3_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.2d, v0.2d, v1.2d}, [x3], #0x30 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I3_I3_1D, ld1_i3_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.1d, v0.1d, v1.1d}, [x3], #0x18 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I4_I4.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I4_I4.S index 9bfd04b3..4f6d2904 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I4_I4.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSEP_I4_I4.S @@ -15,49 +15,121 @@ */ TEST_BEGIN(LD1_ASISDLSEP_I4_I4_16B, ld1_i4_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.16b, v0.16b, v1.16b, v2.16b}, [x3], #0x40 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_8B, ld1_i4_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.8b, v0.8b, v1.8b, v2.8b}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_8H, ld1_i4_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.8h, v0.8h, v1.8h, v2.8h}, [x3], #0x40 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_4H, ld1_i4_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.4h, v0.4h, v1.4h, v2.4h}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_4S, ld1_i4_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [x3], #0x40 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_2S, ld1_i4_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [x3], #0x20 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_2D, ld1_i4_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.2d, v0.2d, v1.2d, v2.2d}, [x3], #0x40 TEST_END TEST_BEGIN(LD1_ASISDLSEP_I4_I4_1D, ld1_i4_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.1d, v0.1d, v1.1d, v2.1d}, [x3], #0x20 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R1_1V.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R1_1V.S index 2cb45c2e..06bc2a8e 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R1_1V.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R1_1V.S @@ -15,49 +15,97 @@ */ TEST_BEGIN(LD1_ASISDLSE_R1_1V_16B, ld1_r1_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v0.16b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_8B, ld1_r1_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.8b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_8H, ld1_r1_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v1.8h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_4H, ld1_r1_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.4h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_4S, ld1_r1_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v0.4s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_2S, ld1_r1_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.2s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_2D, ld1_r1_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] ld1 {v0.2d}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R1_1V_1D, ld1_r1_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] ld1 {v0.1d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R2_2V.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R2_2V.S index 0b94ce20..0eb770ba 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R2_2V.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R2_2V.S @@ -15,49 +15,105 @@ */ TEST_BEGIN(LD1_ASISDLSE_R2_2V_16B, ld1_r2_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] ld1 {v3.16b, v4.16b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_8B, ld1_r2_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld1 {v3.8b, v4.8b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_8H, ld1_r2_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] ld1 {v3.8h, v4.8h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_4H, ld1_r2_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld1 {v3.4h, v4.4h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_4S, ld1_r2_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] ld1 {v3.4s, v4.4s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_2S, ld1_r2_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld1 {v3.2s, v4.2s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_2D, ld1_r2_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] ld1 {v3.2d, v4.2d}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R2_2V_1D, ld1_r2_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld1 {v3.1d, v4.1d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R3_3V.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R3_3V.S index 3f92b906..cbd25057 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R3_3V.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R3_3V.S @@ -15,49 +15,113 @@ */ TEST_BEGIN(LD1_ASISDLSE_R3_3V_16B, ld1_r3_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.16b, v0.16b, v1.16b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_8B, ld1_r3_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.8b, v0.8b, v1.8b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_8H, ld1_r3_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.8h, v0.8h, v1.8h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_4H, ld1_r3_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.4h, v0.4h, v1.4h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_4S, ld1_r3_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.4s, v0.4s, v1.4s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_2S, ld1_r3_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.2s, v0.2s, v1.2s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_2D, ld1_r3_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] ld1 {v31.2d, v0.2d, v1.2d}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R3_3V_1D, ld1_r3_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ld1 {v31.1d, v0.1d, v1.1d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R4_4V.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R4_4V.S index 2f5f2b62..e66a9677 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R4_4V.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSE_R4_4V.S @@ -15,49 +15,121 @@ */ TEST_BEGIN(LD1_ASISDLSE_R4_4V_16B, ld1_r4_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.16b, v0.16b, v1.16b, v2.16b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_8B, ld1_r4_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.8b, v0.8b, v1.8b, v2.8b}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_8H, ld1_r4_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.8h, v0.8h, v1.8h, v2.8h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_4H, ld1_r4_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.4h, v0.4h, v1.4h, v2.4h}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_4S, ld1_r4_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_2S, ld1_r4_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_2D, ld1_r4_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + stp ARG1_64, ARG1_64, [x3, #16] + stp ARG1_64, ARG1_64, [x3, #32] + stp ARG1_64, ARG1_64, [x3, #48] ld1 {v31.2d, v0.2d, v1.2d, v2.2d}, [x3] TEST_END TEST_BEGIN(LD1_ASISDLSE_R4_4V_1D, ld1_r4_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld1 {v31.1d, v0.1d, v1.1d, v2.1d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSOP_SINGLE.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSOP_SINGLE.S new file mode 100644 index 00000000..41ef20ce --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSOP_SINGLE.S @@ -0,0 +1,131 @@ +/* LD1 {.B}[], [], #1 */ +TEST_BEGIN(LD1_ASISDLSOP_B1_I1B, ld1_v0b_post_imm, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + ld1 {v0.b}[0], [x3], #1 + ld1 {v1.b}[3], [x3], #1 + ld1 {v2.b}[7], [x3], #1 +TEST_END + +/* LD1 {.B}[], [], */ +TEST_BEGIN(LD1_ASISDLSOP_BX1_R1B, ld1_v0b_post_reg, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + mov x4, #1 + ld1 {v0.b}[0], [x3], x4 + ld1 {v1.b}[3], [x3], x4 + ld1 {v2.b}[7], [x3], x4 +TEST_END + +/* LD1 {.H}[], [], #2 */ +TEST_BEGIN(LD1_ASISDLSOP_H1_I1H, ld1_v0h_post_imm, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + ld1 {v0.h}[0], [x3], #2 + ld1 {v1.h}[1], [x3], #2 + ld1 {v2.h}[3], [x3], #2 +TEST_END + +/* LD1 {.H}[], [], */ +TEST_BEGIN(LD1_ASISDLSOP_HX1_R1H, ld1_v0h_post_reg, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + mov x4, #2 + ld1 {v0.h}[0], [x3], x4 + ld1 {v1.h}[1], [x3], x4 + ld1 {v2.h}[3], [x3], x4 +TEST_END + +/* LD1 {.S}[], [], #4 */ +TEST_BEGIN(LD1_ASISDLSOP_S1_I1S, ld1_v0s_post_imm, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + ld1 {v0.s}[0], [x3], #4 + ld1 {v1.s}[1], [x3], #4 + ld1 {v2.s}[2], [x3], #4 +TEST_END + +/* LD1 {.S}[], [], */ +TEST_BEGIN(LD1_ASISDLSOP_SX1_R1S, ld1_v0s_post_reg, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + mov x4, #4 + ld1 {v0.s}[0], [x3], x4 + ld1 {v1.s}[1], [x3], x4 + ld1 {v2.s}[2], [x3], x4 +TEST_END + +/* LD1 {.D}[], [], #8 */ +TEST_BEGIN(LD1_ASISDLSOP_D1_I1D, ld1_v0d_post_imm, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + ld1 {v0.d}[0], [x3], #8 + ld1 {v1.d}[1], [x3], #8 +TEST_END + +/* LD1 {.D}[], [], */ +TEST_BEGIN(LD1_ASISDLSOP_DX1_R1D, ld1_v0d_post_reg, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + mov x4, #8 + ld1 {v0.d}[0], [x3], x4 + ld1 {v1.d}[1], [x3], x4 +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSO_SINGLE.S b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSO_SINGLE.S new file mode 100644 index 00000000..fabb5740 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/LD1_ASISDLSO_SINGLE.S @@ -0,0 +1,58 @@ +/* LD1 {.B}[], [] */ +TEST_BEGIN(LD1_ASISDLSO_B1_1B, ld1_v0b_idx0, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1 {v0.b}[0], [x3] + ld1 {v1.b}[3], [x3] + ld1 {v2.b}[7], [x3] +TEST_END + +/* LD1 {.H}[], [] */ +TEST_BEGIN(LD1_ASISDLSO_H1_1H, ld1_v0h_idx0, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1 {v0.h}[0], [x3] + ld1 {v1.h}[1], [x3] + ld1 {v2.h}[3], [x3] +TEST_END + +/* LD1 {.S}[], [] */ +TEST_BEGIN(LD1_ASISDLSO_S1_1S, ld1_v0s_idx0, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1 {v0.s}[0], [x3] + ld1 {v1.s}[1], [x3] + ld1 {v2.s}[2], [x3] +TEST_END + +/* LD1 {.D}[], [] */ +TEST_BEGIN(LD1_ASISDLSO_D1_1D, ld1_v0d_idx0, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + str ARG1_64, [x3] + ld1 {v0.d}[0], [x3] + ld1 {v1.d}[1], [x3] +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSEP_I2_I.S b/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSEP_I2_I.S index c28028a2..c6e2b075 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSEP_I2_I.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSEP_I2_I.S @@ -15,43 +15,100 @@ */ TEST_BEGIN(LD2_ASISDLSEP_I2_I_16B, ld2_i2_i_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.16b, v4.16b}, [x3], #32 TEST_END TEST_BEGIN(LD2_ASISDLSEP_I2_I_8B, ld2_i2_i_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld2 {v3.8b, v4.8b}, [x3], #16 TEST_END TEST_BEGIN(LD2_ASISDLSEP_I2_I_4H, ld2_i2_i_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld2 {v3.4h, v4.4h}, [x3], #16 TEST_END TEST_BEGIN(LD2_ASISDLSEP_I2_I_8H, ld2_i2_i_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.8h, v4.8h}, [x3], #32 TEST_END TEST_BEGIN(LD2_ASISDLSEP_I2_I_4S, ld2_i2_i_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.4s, v4.4s}, [x3], #32 TEST_END TEST_BEGIN(LD2_ASISDLSEP_I2_I_2S, ld2_i2_i_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld2 {v3.2s, v4.2s}, [x3], #16 TEST_END TEST_BEGIN(LD2_ASISDLSEP_I2_I_2D, ld2_i2_i_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.2d, v4.2d}, [x3], #32 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSE_R2.S b/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSE_R2.S index 359d18ff..1455014b 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSE_R2.S +++ b/backend/remill/tests/AArch64/DATAXFER/LD2_ASISDLSE_R2.S @@ -15,43 +15,100 @@ */ TEST_BEGIN(LD2_ASISDLSE_R2_16B, ld2_r2_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.16b, v4.16b}, [x3] TEST_END TEST_BEGIN(LD2_ASISDLSE_R2_8B, ld2_r2_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld2 {v3.8b, v4.8b}, [x3] TEST_END TEST_BEGIN(LD2_ASISDLSE_R2_4H, ld2_r2_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld2 {v3.4h, v4.4h}, [x3] TEST_END TEST_BEGIN(LD2_ASISDLSE_R2_8H, ld2_r2_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.8h, v4.8h}, [x3] TEST_END TEST_BEGIN(LD2_ASISDLSE_R2_4S, ld2_r2_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.4s, v4.4s}, [x3] TEST_END TEST_BEGIN(LD2_ASISDLSE_R2_2S, ld2_r2_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] ld2 {v3.2s, v4.2s}, [x3] TEST_END TEST_BEGIN(LD2_ASISDLSE_R2_2D, ld2_r2_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] ld2 {v3.2d, v4.2d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_OFF.S b/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_OFF.S index c1f77a99..73a8f88e 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_OFF.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_OFF.S @@ -16,32 +16,69 @@ /* LDP , , [{, #}] */ TEST_BEGIN(LDP_32_LDSTPAIR_OFF, ldp_w0_w1_m64_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #72] ldp w4, w5, [x3, #0] ldp w6, w7, [x3, #32] ldp w8, w9, [x3, #64] TEST_END TEST_BEGIN(LDP_32_LDSTPAIR_OFF, ldp_w3_w5_m64_off_nowb, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] ldp w3, w5, [x3, #0] TEST_END TEST_BEGIN(LDP_32_LDSTPAIR_OFF, ldp_w4_w3_m64_off_nowb, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] ldp w4, w3, [x3, #0] TEST_END /* LDP , , [{, #}] */ TEST_BEGIN(LDP_64_LDSTPAIR_OFF, ldp_x0_x1_m128_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #72] ldp x4, x5, [x3, #0] ldp x6, x7, [x3, #32] ldp x8, x9, [x3, #64] @@ -49,9 +86,20 @@ TEST_END /* LDP , , [{, #}] */ TEST_BEGIN(LDP_S_LDSTPAIR_OFF, ldp_s0_s1_m64_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #72] ldp s0, s1, [x3, #0] ldp s2, s3, [x3, #32] ldp s4, s5, [x3, #64] @@ -59,9 +107,20 @@ TEST_END /* LDP , , [{, #}] */ TEST_BEGIN(LDP_D_LDSTPAIR_OFF, ldp_d0_d1_m128_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #72] ldp d0, d1, [x3, #0] ldp d2, d3, [x3, #32] ldp d4, d5, [x3, #64] @@ -69,9 +128,26 @@ TEST_END /* LDP , , [{, #}] */ TEST_BEGIN(LDP_Q_LDSTPAIR_OFF, ldp_q0_q1_m256_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #48] + str ARG1_64, [x3, #56] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #72] + str ARG1_64, [x3, #80] + str ARG1_64, [x3, #88] ldp q0, q1, [x3, #0] ldp q2, q3, [x3, #32] ldp q4, q5, [x3, #64] diff --git a/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_POST.S b/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_POST.S index 6df9ce2d..7e51cdcd 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_POST.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_POST.S @@ -16,9 +16,20 @@ /* LDP , , [], # */ TEST_BEGIN(LDP_32_LDSTPAIR_POST, ldp_w0_w1_m64_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp w4, w5, [x3], #0 ldp w6, w7, [x3], #32 ldp w8, w9, [x3], #64 @@ -26,9 +37,20 @@ TEST_END /* LDP , , [], # */ TEST_BEGIN(LDP_64_LDSTPAIR_POST, ldp_x0_x1_m128_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp x4, x5, [x3], #0 ldp x6, x7, [x3], #32 ldp x8, x9, [x3], #64 @@ -36,9 +58,20 @@ TEST_END /* LDP , , [], # */ TEST_BEGIN(LDP_S_LDSTPAIR_POST, ldp_s0_s1_m64_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp s4, s5, [x3], #0 ldp s6, s7, [x3], #32 ldp s8, s9, [x3], #64 @@ -46,9 +79,20 @@ TEST_END /* LDP , , [], # */ TEST_BEGIN(LDP_D_LDSTPAIR_POST, ldp_d0_d1_m128_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp d4, d5, [x3], #0 ldp d6, d7, [x3], #32 ldp d8, d9, [x3], #64 @@ -56,9 +100,26 @@ TEST_END /* LDP , , [], # */ TEST_BEGIN(LDP_Q_LDSTPAIR_POST, ldp_q0_q1_m256_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #48] + str ARG1_64, [x3, #56] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] + str ARG1_64, [x3, #112] + str ARG1_64, [x3, #120] ldp q4, q5, [x3], #0 ldp q6, q7, [x3], #32 ldp q8, q9, [x3], #64 diff --git a/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_PRE.S b/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_PRE.S index 9ce14ff7..832a02be 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_PRE.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDP_n_LDSTPAIR_PRE.S @@ -16,9 +16,20 @@ /* LDP , , [, #]! */ TEST_BEGIN(LDP_32_LDSTPAIR_PRE, ldp_w0_w1_m64_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp w4, w5, [x3, #0]! ldp w6, w7, [x3, #32]! ldp w8, w9, [x3, #64]! @@ -26,9 +37,20 @@ TEST_END /* LDP , , [, #]! */ TEST_BEGIN(LDP_64_LDSTPAIR_PRE, ldp_x0_x1_m128_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp x4, x5, [x3, #0]! ldp x6, x7, [x3, #32]! ldp x8, x9, [x3, #64]! @@ -36,9 +58,20 @@ TEST_END /* LDP , , [, #]! */ TEST_BEGIN(LDP_S_LDSTPAIR_PRE, ldp_s0_s1_m64_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp s4, s5, [x3, #0]! ldp s6, s7, [x3, #32]! ldp s8, s9, [x3, #64]! @@ -46,9 +79,20 @@ TEST_END /* LDP , , [, #]! */ TEST_BEGIN(LDP_D_LDSTPAIR_PRE, ldp_d0_d1_m128_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] ldp d4, d5, [x3, #0]! ldp d6, d7, [x3, #32]! ldp d8, d9, [x3, #64]! @@ -56,12 +100,27 @@ TEST_END /* LDP , , [, #]! */ TEST_BEGIN(LDP_Q_LDSTPAIR_PRE, ldp_q0_q1_m256_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] + str ARG1_64, [x3, #48] + str ARG1_64, [x3, #56] + str ARG1_64, [x3, #96] + str ARG1_64, [x3, #104] + str ARG1_64, [x3, #112] + str ARG1_64, [x3, #120] ldp q4, q5, [x3, #0]! ldp q6, q7, [x3, #32]! ldp q8, q9, [x3, #64]! TEST_END - - diff --git a/backend/remill/tests/AArch64/DATAXFER/LDRB.S b/backend/remill/tests/AArch64/DATAXFER/LDRB.S index 62c8068f..467bb1a8 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDRB.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDRB.S @@ -16,8 +16,16 @@ /* LDRB , [{, #}] */ TEST_BEGIN(LDRB_32_LDST_POS, ldrb_w563_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrb w5, [x3] ldrb w6, [x3, #16] ldrb w3, [x3, #32] @@ -25,8 +33,15 @@ TEST_END /* LDRB , [], # */ TEST_BEGIN(LDRB_32_LDST_IMMPOST, ldrb_w56_m8_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrb w5, [x3], #0 ldrb w6, [x3], #32 TEST_END @@ -49,8 +64,14 @@ TEST_END /* LDRB , [, #]! */ TEST_BEGIN(LDRB_32_LDST_IMMPRE, ldrb_w5_m8_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrb w5, [x3, #16]! TEST_END @@ -83,8 +104,18 @@ TEST_END /* LDRB , [, {, LSL }] */ TEST_BEGIN(LDRB_32BL_LDST_REGOFF, ldrb_w5_m8_off_w0_lsl0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #64] ldrb w5, [x3, ARG1_64] /* Implicit LSL 0 */ ldrb w5, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LDRH.S b/backend/remill/tests/AArch64/DATAXFER/LDRH.S index b8ce567d..4cdc21ed 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDRH.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDRH.S @@ -16,8 +16,16 @@ /* LDRH , [{, #}] */ TEST_BEGIN(LDRH_32_LDST_POS, ldrh_w563_m16, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrh w5, [x3] ldrh w6, [x3, #16] ldrh w3, [x3, #32] @@ -25,8 +33,15 @@ TEST_END /* LDRH , [], # */ TEST_BEGIN(LDRH_32_LDST_IMMPOST, ldrh_w56_m16_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrh w5, [x3], #0 ldrh w6, [x3], #32 TEST_END @@ -39,8 +54,14 @@ TEST_END /* LDRH , [, #]! */ TEST_BEGIN(LDRH_32_LDST_IMMPRE, ldrh_w5_m16_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrh w5, [x3, #16]! TEST_END @@ -67,8 +88,19 @@ TEST_END /* LDRH , [, {, LSL }] */ TEST_BEGIN(LDRH_32_LDST_REGOFF, ldrh_w567_m16_off_w0_lsl01, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #128] ldrh w5, [x3, ARG1_64] /* Implicit LSL 0 */ ldrh w6, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ ldrh w7, [x3, ARG1_64, lsl #1] /* Explicit LSL 1 */ diff --git a/backend/remill/tests/AArch64/DATAXFER/LDRSB.S b/backend/remill/tests/AArch64/DATAXFER/LDRSB.S index a7981f2d..8848e9ea 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDRSB.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDRSB.S @@ -16,8 +16,16 @@ /* LDRSB , [{, #}] */ TEST_BEGIN(LDRSB_32_LDST_POS, ldrsb_w563_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrsb w5, [x3] ldrsb w6, [x3, #16] ldrsb w3, [x3, #32] @@ -25,8 +33,16 @@ TEST_END /* LDRSB , [{, #}] */ TEST_BEGIN(LDRSB_64_LDST_POS, ldrsb_x563_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrsb x5, [x3] ldrsb x6, [x3, #16] ldrsb x3, [x3, #32] @@ -34,16 +50,30 @@ TEST_END /* LDRSB , [], # */ TEST_BEGIN(LDRSB_32_LDST_IMMPOST, ldrsb_w56_m8_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrsb w5, [x3], #0 ldrsb w6, [x3], #32 TEST_END /* LDRSB , [], # */ TEST_BEGIN(LDRSB_64_LDST_IMMPOST, ldrsb_x56_m8_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrsb x5, [x3], #0 ldrsb x6, [x3], #32 TEST_END @@ -62,15 +92,27 @@ TEST_END /* LDRSB , [, #]! */ TEST_BEGIN(LDRSB_32_LDST_IMMPRE, ldrsb_w5_m8_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrsb w5, [x3, #16]! TEST_END /* LDRSB , [, #]! */ TEST_BEGIN(LDRSB_64_LDST_IMMPRE, ldrsb_x5_m8_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrsb x5, [x3, #16]! TEST_END @@ -114,15 +156,35 @@ TEST_END /* LDRSB , [, {, LSL }] */ TEST_BEGIN(LDRSB_32BL_LDST_REGOFF, ldrsb_w56_m8_off_w0_lsl0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #64] ldrsb w5, [x3, ARG1_64] /* Implicit LSL 0 */ ldrsb w6, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ TEST_END TEST_BEGIN(LDRSB_64BL_LDST_REGOFF, ldrsb_x56_m8_off_w0_lsl0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #64] ldrsb x5, [x3, ARG1_64] /* Implicit LSL 0 */ ldrsb x6, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LDRSH.S b/backend/remill/tests/AArch64/DATAXFER/LDRSH.S index 0f51ce28..ff4ff3b7 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDRSH.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDRSH.S @@ -16,8 +16,16 @@ /* LDRSH , [{, #}] */ TEST_BEGIN(LDRSH_32_LDST_POS, ldrsh_w563_m16, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrsh w5, [x3] ldrsh w6, [x3, #16] ldrsh w3, [x3, #32] @@ -25,8 +33,16 @@ TEST_END /* LDRSH , [{, #}] */ TEST_BEGIN(LDRSH_64_LDST_POS, ldrsh_x563_m16, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrsh x5, [x3] ldrsh x6, [x3, #16] ldrsh x3, [x3, #32] @@ -34,16 +50,30 @@ TEST_END /* LDRSH , [], # */ TEST_BEGIN(LDRSH_32_LDST_IMMPOST, ldrsh_w56_m16_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrsh w5, [x3], #0 ldrsh w6, [x3], #32 TEST_END /* LDRSH , [], # */ TEST_BEGIN(LDRSH_64_LDST_IMMPOST, ldrsh_x56_m16_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrsh x5, [x3], #0 ldrsh x6, [x3], #32 TEST_END @@ -62,15 +92,27 @@ TEST_END /* LDRSH , [, #]! */ TEST_BEGIN(LDRSH_32_LDST_IMMPRE, ldrsh_w5_m16_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrsh w5, [x3, #16]! TEST_END /* LDRSH , [, #]! */ TEST_BEGIN(LDRSH_64_LDST_IMMPRE, ldrsh_x5_m16_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrsh x5, [x3, #16]! TEST_END @@ -118,27 +160,47 @@ TEST_END /* LDRSH , [, {, LSL }] */ TEST_BEGIN(LDRSH_32_LDST_REGOFF, ldrsh_w5_m16_off_w0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 ldrsh w5, [x3, ARG1_64] /* Implicit LSL 0 */ TEST_END /* LDRSH , [, {, LSL }] */ TEST_BEGIN(LDRSH_64_LDST_REGOFF, ldrsh_x5_m16_off_w0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 ldrsh x5, [x3, ARG1_64] /* Implicit LSL 0 */ TEST_END TEST_BEGIN(LDRSH_32_LDST_REGOFF, ldrsh_w56_m16_off_w0_lsl01, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 ldrsh w5, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ ldrsh w6, [x3, ARG1_64, lsl #1] /* Explicit LSL 1 */ TEST_END TEST_BEGIN(LDRSH_64_LDST_REGOFF, ldrsh_x56_m16_off_w0_lsl01, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 ldrsh x5, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ ldrsh x6, [x3, ARG1_64, lsl #1] /* Explicit LSL 1 */ diff --git a/backend/remill/tests/AArch64/DATAXFER/LDRSW.S b/backend/remill/tests/AArch64/DATAXFER/LDRSW.S index 25cef93d..d51adadb 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDRSW.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDRSW.S @@ -16,8 +16,16 @@ /* LDRSW , [{, #}] */ TEST_BEGIN(LDRSW_64_LDST_POS, ldrsw_x563_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldrsw x5, [x3] ldrsw x6, [x3, #16] ldrsw x3, [x3, #32] @@ -25,8 +33,15 @@ TEST_END /* LDRSW , [], # */ TEST_BEGIN(LDRSW_64_LDST_IMMPOST, ldrsw_x56_m32_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #32] ldrsw x5, [x3], #0 ldrsw x6, [x3], #32 TEST_END @@ -39,8 +54,14 @@ TEST_END /* LDRSW , [, #]! */ TEST_BEGIN(LDRSW_64_LDST_IMMPRE, ldrsw_x5_m32_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) add x3, sp, #-256 + str ARG1_64, [x3, #16] ldrsw x5, [x3, #16]! TEST_END @@ -66,8 +87,19 @@ TEST_INPUTS( TEST_END TEST_BEGIN(LDRSW_64_LDST_REGOFF, ldrsw_x567_m32_off_w0_lsl02, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #64] + str ARG1_64, [x3, #128] ldrsw x5, [x3, ARG1_64] /* Implicit LSL 0 */ ldrsw x6, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ ldrsw x7, [x3, ARG1_64, lsl #2] /* Explicit LSL 2 */ diff --git a/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPOST.S b/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPOST.S index aed6c332..d5472f5f 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPOST.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPOST.S @@ -8,59 +8,121 @@ * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * dildributed under the License is dildributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either expostss or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ TEST_BEGIN(LDR_32_LDST_IMMPOST, ldr_w5_m32_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldr w5, [x3], #0 TEST_END TEST_BEGIN(LDR_64_LDST_IMMPOST, ldr_x5_m64_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldr x5, [x3], #0 TEST_END TEST_BEGIN(LDR_B_LDST_IMMPOST, ldr_b0_m8_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr b0, [x3], #0 ldr b1, [x3], #16 ldr b3, [x3], #32 TEST_END TEST_BEGIN(LDR_H_LDST_IMMPOST, ldr_h0_m16_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr h0, [x3], #0 ldr h1, [x3], #16 ldr h3, [x3], #32 TEST_END TEST_BEGIN(LDR_S_LDST_IMMPOST, ldr_s0_m32_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr s0, [x3], #0 ldr s1, [x3], #16 ldr s3, [x3], #32 TEST_END TEST_BEGIN(LDR_D_LDST_IMMPOST, ldr_d0_m64_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr d0, [x3], #0 ldr d1, [x3], #16 ldr d3, [x3], #32 TEST_END TEST_BEGIN(LDR_Q_LDST_IMMPOST, ldr_q0_m128_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] + str ARG1_64, [x3, #48] + str ARG1_64, [x3, #56] ldr q0, [x3], #0 ldr q1, [x3], #16 ldr q3, [x3], #32 diff --git a/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPRE.S b/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPRE.S index 2c958887..680ebcc0 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPRE.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_IMMPRE.S @@ -8,59 +8,121 @@ * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * dildributed under the License is dildributed on an "AS IS" BASIS, + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ TEST_BEGIN(LDR_32_LDST_IMMPRE, ldr_w5_m32_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldr w5, [x3, #0]! TEST_END TEST_BEGIN(LDR_64_LDST_IMMPRE, ldr_x5_m64_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldr x5, [x3, #0]! TEST_END TEST_BEGIN(LDR_B_LDST_IMMPRE, ldr_b0_m8_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr b0, [x3, #0]! ldr b1, [x3, #16]! ldr b3, [x3, #32]! TEST_END TEST_BEGIN(LDR_H_LDST_IMMPRE, ldr_h0_m16_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr h0, [x3, #0]! ldr h1, [x3, #16]! ldr h3, [x3, #32]! TEST_END TEST_BEGIN(LDR_S_LDST_IMMPRE, ldr_s0_m32_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr s0, [x3, #0]! ldr s1, [x3, #16]! ldr s3, [x3, #32]! TEST_END TEST_BEGIN(LDR_D_LDST_IMMPRE, ldr_d0_m64_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #48] ldr d0, [x3, #0]! ldr d1, [x3, #16]! ldr d3, [x3, #32]! TEST_END TEST_BEGIN(LDR_Q_LDST_IMMPRE, ldr_q0_m128_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] + str ARG1_64, [x3, #48] + str ARG1_64, [x3, #56] ldr q0, [x3, #0]! ldr q1, [x3, #16]! ldr q3, [x3, #32]! diff --git a/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_POS.S b/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_POS.S index 56beab7a..9278f2e8 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_POS.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDR_n_LDST_POS.S @@ -8,59 +8,121 @@ * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * dildributed under the License is dildributed on an "AS IS" BASIS, + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ TEST_BEGIN(LDR_32_LDST_POS, ldr_w5_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldr w5, [x3, #0] TEST_END TEST_BEGIN(LDR_64_LDST_POS, ldr_x5_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldr x5, [x3, #0] TEST_END TEST_BEGIN(LDR_B_LDST_POS, ldr_b0_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldr b0, [x3, #0] ldr b1, [x3, #16] ldr b3, [x3, #32] TEST_END TEST_BEGIN(LDR_H_LDST_POS, ldr_h0_m16, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldr h0, [x3, #0] ldr h1, [x3, #16] ldr h3, [x3, #32] TEST_END TEST_BEGIN(LDR_S_LDST_POS, ldr_s0_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldr s0, [x3, #0] ldr s1, [x3, #16] ldr s3, [x3, #32] TEST_END TEST_BEGIN(LDR_D_LDST_POS, ldr_d0_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] ldr d0, [x3, #0] ldr d1, [x3, #16] ldr d3, [x3, #32] TEST_END TEST_BEGIN(LDR_Q_LDST_POS, ldr_q0_m128, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #24] + str ARG1_64, [x3, #32] + str ARG1_64, [x3, #40] ldr q0, [x3, #0] ldr q1, [x3, #16] ldr q3, [x3, #32] diff --git a/backend/remill/tests/AArch64/DATAXFER/LDUR_FP_LDST_UNSCALED.S b/backend/remill/tests/AArch64/DATAXFER/LDUR_FP_LDST_UNSCALED.S new file mode 100644 index 00000000..b826c91c --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/LDUR_FP_LDST_UNSCALED.S @@ -0,0 +1,89 @@ +/* LDUR , [{, #}] */ +TEST_BEGIN(LDUR_B_LDST_UNSCALED, ldur_b0_unscaled, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304, + 0xABCDEF0123456789) + add x3, sp, #-256 + str ARG1_64, [x3] + ldur b0, [x3, #0] + ldur b1, [x3, #1] + ldur b2, [x3, #2] +TEST_END + +/* LDUR , [{, #}] */ +TEST_BEGIN(LDUR_H_LDST_UNSCALED, ldur_h0_unscaled, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304, + 0xABCDEF0123456789) + add x3, sp, #-256 + str ARG1_64, [x3] + ldur h0, [x3, #0] + ldur h1, [x3, #2] + ldur h2, [x3, #4] +TEST_END + +/* LDUR , [{, #}] */ +TEST_BEGIN(LDUR_S_LDST_UNSCALED, ldur_s0_unscaled, 1) +TEST_INPUTS( + 0x3F80000040000000, + 0x7F800000FF800000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x41414141ABABABAB, + 0x7FF8000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + ldur s0, [x3, #0] + ldur s1, [x3, #4] +TEST_END + +/* LDUR
, [{, #}] */ +TEST_BEGIN(LDUR_D_LDST_UNSCALED, ldur_d0_unscaled, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0xFFF0000000000000, + 0x4141414141414141) + add x3, sp, #-256 + str ARG1_64, [x3] + ldur d0, [x3, #0] +TEST_END + +/* LDUR , [{, #}] */ +TEST_BEGIN(LDUR_Q_LDST_UNSCALED, ldur_q0_unscaled, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0xFFF0000000000000, + 0x4141414141414141) + add x3, sp, #-256 + stp ARG1_64, ARG1_64, [x3] + ldur q0, [x3, #0] +TEST_END + +/* LDURSH , [{, #}] */ +TEST_BEGIN(LDURSH_64_LDST_UNSCALED, ldursh_x0_unscaled, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x000000000000FFFF, + 0x0000000000008000, + 0x0000000000007FFF, + 0x0000000000000000, + 0x00000000000000FF) + add x3, sp, #-256 + str ARG1_64, [x3] + ldursh x0, [x3, #0] + ldursh x1, [x3, #0] +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/LDUR_n_LDST_UNSCALED.S b/backend/remill/tests/AArch64/DATAXFER/LDUR_n_LDST_UNSCALED.S index 8796676d..f52f5919 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDUR_n_LDST_UNSCALED.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDUR_n_LDST_UNSCALED.S @@ -16,8 +16,17 @@ /* LDURB , [{, #}] */ TEST_BEGIN(LDURB_32_LDST_UNSCALED, ldurb_w5_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ldurb w5, [x3, #0] ldurb w6, [x3, #8] ldurb w7, [x3, #16] @@ -25,8 +34,17 @@ TEST_END /* LDURH , [{, #}] */ TEST_BEGIN(LDURH_32_LDST_UNSCALED, ldurh_w5_m16, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ldurh w5, [x3, #0] ldurh w6, [x3, #8] ldurh w7, [x3, #16] @@ -34,8 +52,17 @@ TEST_END /* LDUR , [{, #}] */ TEST_BEGIN(LDUR_32_LDST_UNSCALED, ldur_w5_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ldur w5, [x3, #0] ldur w6, [x3, #8] ldur w7, [x3, #16] @@ -43,8 +70,17 @@ TEST_END /* LDUR , [{, #}] */ TEST_BEGIN(LDUR_64_LDST_UNSCALED, ldur_x5_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] + str ARG1_64, [x3, #8] + str ARG1_64, [x3, #16] ldur x5, [x3, #0] ldur x6, [x3, #8] ldur x7, [x3, #16] diff --git a/backend/remill/tests/AArch64/DATAXFER/LDXR_LRn_LDSTEXCL.S b/backend/remill/tests/AArch64/DATAXFER/LDXR_LRn_LDSTEXCL.S index 77eeef73..8bd2c03b 100644 --- a/backend/remill/tests/AArch64/DATAXFER/LDXR_LRn_LDSTEXCL.S +++ b/backend/remill/tests/AArch64/DATAXFER/LDXR_LRn_LDSTEXCL.S @@ -8,22 +8,36 @@ * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * dildributed under the License is dildributed on an "AS IS" BASIS, + * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ TEST_BEGIN(LDXR_LR32_LDSTEXCL, ldxr_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldxr w5, [x3] - ldxr w6, [x3, #0] + ldxr w6, [x3] TEST_END TEST_BEGIN(LDXR_LR64_LDSTEXCL, ldxr_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0xababababcdcdcdcd, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000001) + add x3, sp, #-256 + str ARG1_64, [x3] ldxr x5, [x3] - ldxr x6, [x3, #0] + ldxr x6, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/MOVN_n_MOVEWIDE.S b/backend/remill/tests/AArch64/DATAXFER/MOVN_n_MOVEWIDE.S new file mode 100644 index 00000000..d6a64067 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/MOVN_n_MOVEWIDE.S @@ -0,0 +1,24 @@ +TEST_BEGIN(MOVN_32_MOVEWIDE, movn_w9_0, 1) +TEST_INPUTS(0) + movn w9, #0 +TEST_END + +TEST_BEGIN(MOVN_32_MOVEWIDE, movn_w9_0x1234, 1) +TEST_INPUTS(0) + movn w9, #0x1234 +TEST_END + +TEST_BEGIN(MOVN_64_MOVEWIDE, movn_x9_0, 1) +TEST_INPUTS(0) + movn x9, #0 +TEST_END + +TEST_BEGIN(MOVN_64_MOVEWIDE, movn_x9_0x1234, 1) +TEST_INPUTS(0) + movn x9, #0x1234 +TEST_END + +TEST_BEGIN(MOVN_64_MOVEWIDE, movn_x9_0x1234_lsl16, 1) +TEST_INPUTS(0) + movn x9, #0x1234, lsl #16 +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/SMOV.S b/backend/remill/tests/AArch64/DATAXFER/SMOV.S index fbfc7dcd..af85be44 100644 --- a/backend/remill/tests/AArch64/DATAXFER/SMOV.S +++ b/backend/remill/tests/AArch64/DATAXFER/SMOV.S @@ -16,7 +16,15 @@ /* SMOV , .[] */ TEST_BEGIN(SMOV_ASIMDINS_W_W_B, smov_wN_B, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0102030405060708, + 0x7f80ff00deadbeef, + 0xffffffffffffffff, + 0x8000000000000000, + 0x0080007f00ff0001) + + fmov d0, ARG1_64 smov w0, v0.B[0] smov w1, v0.B[4] smov w2, v0.B[8] @@ -24,7 +32,15 @@ TEST_INPUTS(0) TEST_END TEST_BEGIN(SMOV_ASIMDINS_W_W_H, smov_wN_H, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0001000200030004, + 0x7fff800000ff00fe, + 0xffffffffffffffff, + 0x8000000000000000, + 0x00807fff0001fffe) + + fmov d0, ARG1_64 smov w0, v0.H[0] smov w1, v0.H[2] smov w2, v0.H[4] @@ -35,7 +51,15 @@ TEST_END /* SMOV , .[] */ TEST_BEGIN(SMOV_ASIMDINS_X_X_B, smov_xN_B, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0102030405060708, + 0x7f80ff00deadbeef, + 0xffffffffffffffff, + 0x8000000000000000, + 0x0080007f00ff0001) + + fmov d0, ARG1_64 smov x0, v0.B[0] smov x1, v0.B[4] smov x2, v0.B[8] @@ -43,7 +67,15 @@ TEST_INPUTS(0) TEST_END TEST_BEGIN(SMOV_ASIMDINS_X_X_H, smov_xN_H, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0001000200030004, + 0x7fff800000ff00fe, + 0xffffffffffffffff, + 0x8000000000000000, + 0x00807fff0001fffe) + + fmov d0, ARG1_64 smov x0, v0.H[0] smov x1, v0.H[2] smov x2, v0.H[4] @@ -51,7 +83,15 @@ TEST_INPUTS(0) TEST_END TEST_BEGIN(SMOV_ASIMDINS_X_X_S, smov_xN_S, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x000000017fffffff, + 0x80000000ffffffff, + 0xffffffffffffffff, + 0x8000000000000000, + 0x7fffffff00000001) + + fmov d0, ARG1_64 smov x0, v0.S[0] smov x1, v0.S[1] smov x2, v0.S[2] diff --git a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSEP_I2_I2.S b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSEP_I2_I2.S index 1fd90c4b..bb40a4ae 100644 --- a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSEP_I2_I2.S +++ b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSEP_I2_I2.S @@ -15,57 +15,129 @@ */ TEST_BEGIN(ST1_ASISDLSEP_I2_I2_16B, st1_i2_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.16b, v4.16b}, [x3], #0x20 st1 {v31.16b, v0.16b}, [x3], #0x20 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_8B, st1_i2_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.8b, v4.8b}, [x3], #0x10 st1 {v31.8b, v0.8b}, [x3], #0x10 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_8H, st1_i2_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.8h, v4.8h}, [x3], #0x20 st1 {v31.8h, v0.8h}, [x3], #0x20 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_4H, st1_i2_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.4h, v4.4h}, [x3], #0x10 st1 {v31.4h, v0.4h}, [x3], #0x10 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_4S, st1_i2_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.4s, v4.4s}, [x3], #0x20 st1 {v31.4s, v0.4s}, [x3], #0x20 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_2S, st1_i2_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.2s, v4.2s}, [x3], #0x10 st1 {v31.2s, v0.2s}, [x3], #0x10 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_2D, st1_i2_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.2d, v4.2d}, [x3], #0x20 st1 {v31.2d, v0.2d}, [x3], #0x20 TEST_END TEST_BEGIN(ST1_ASISDLSEP_I2_I2_1D, st1_i2_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 + dup v31.2d, ARG1_64 + dup v0.2d, ARG1_64 st1 {v3.1d, v4.1d}, [x3], #0x10 st1 {v31.1d, v0.1d}, [x3], #0x10 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R1_1V.S b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R1_1V.S index 4016c7d3..433786a8 100644 --- a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R1_1V.S +++ b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R1_1V.S @@ -15,52 +15,100 @@ */ TEST_BEGIN(ST1_ASISDLSE_R1_1V_16B, st1_r1_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.16b}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_8B, st1_r1_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.8b}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_8H, st1_r1_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.8h}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_4H, st1_r1_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.4h}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_4S, st1_r1_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.4s}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_2S, st1_r1_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.2s}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_2D, st1_r1_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.2d}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R1_1V_1D, st1_r1_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 st1 {v0.1d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R2_2V.S b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R2_2V.S index 26c225f6..68e971e0 100644 --- a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R2_2V.S +++ b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSE_R2_2V.S @@ -15,57 +15,105 @@ */ TEST_BEGIN(ST1_ASISDLSE_R2_2V_16B, st1_r2_16b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.16b, v4.16b}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_8B, st1_r2_8b, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.8b, v4.8b}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_4H, st1_r2_4h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.4h, v4.4h}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_8H, st1_r2_8h, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.8h, v4.8h}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_2S, st1_r2_2s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.2s, v4.2s}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_4S, st1_r2_4s, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.4s, v4.4s}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_1D, st1_r2_1d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.1d, v4.1d}, [x3] TEST_END TEST_BEGIN(ST1_ASISDLSE_R2_2V_2D, st1_r2_2d, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 - movi v3.2s, #255 + dup v3.2d, ARG1_64 + dup v4.2d, ARG1_64 st1 {v3.2d, v4.2d}, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSOP_SINGLE.S b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSOP_SINGLE.S new file mode 100644 index 00000000..02661573 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSOP_SINGLE.S @@ -0,0 +1,117 @@ +/* ST1 {.B}[], [], #1 */ +TEST_BEGIN(ST1_ASISDLSOP_B1_I1B, st1_v0b_post_imm, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.b}[0], [x3], #1 + st1 {v0.b}[3], [x3], #1 + st1 {v0.b}[7], [x3], #1 +TEST_END + +/* ST1 {.B}[], [], */ +TEST_BEGIN(ST1_ASISDLSOP_BX1_R1B, st1_v0b_post_reg, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + fmov d0, ARG1_64 + mov x4, #1 + st1 {v0.b}[0], [x3], x4 + st1 {v0.b}[3], [x3], x4 + st1 {v0.b}[7], [x3], x4 +TEST_END + +/* ST1 {.H}[], [], #2 */ +TEST_BEGIN(ST1_ASISDLSOP_H1_I1H, st1_v0h_post_imm, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.h}[0], [x3], #2 + st1 {v0.h}[1], [x3], #2 + st1 {v0.h}[3], [x3], #2 +TEST_END + +/* ST1 {.H}[], [], */ +TEST_BEGIN(ST1_ASISDLSOP_HX1_R1H, st1_v0h_post_reg, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + fmov d0, ARG1_64 + mov x4, #2 + st1 {v0.h}[0], [x3], x4 + st1 {v0.h}[1], [x3], x4 + st1 {v0.h}[3], [x3], x4 +TEST_END + +/* ST1 {.S}[], [], #4 */ +TEST_BEGIN(ST1_ASISDLSOP_S1_I1S, st1_v0s_post_imm, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.s}[0], [x3], #4 + st1 {v0.s}[1], [x3], #4 +TEST_END + +/* ST1 {.S}[], [], */ +TEST_BEGIN(ST1_ASISDLSOP_SX1_R1S, st1_v0s_post_reg, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + mov x4, #4 + st1 {v0.s}[0], [x3], x4 + st1 {v0.s}[1], [x3], x4 +TEST_END + +/* ST1 {.D}[], [], #8 */ +TEST_BEGIN(ST1_ASISDLSOP_D1_I1D, st1_v0d_post_imm, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.d}[0], [x3], #8 +TEST_END + +/* ST1 {.D}[], [], */ +TEST_BEGIN(ST1_ASISDLSOP_DX1_R1D, st1_v0d_post_reg, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + fmov d0, ARG1_64 + mov x4, #8 + st1 {v0.d}[0], [x3], x4 +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSO_SINGLE.S b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSO_SINGLE.S new file mode 100644 index 00000000..a51e8ba2 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/ST1_ASISDLSO_SINGLE.S @@ -0,0 +1,56 @@ +/* ST1 {.B}[], [] */ +TEST_BEGIN(ST1_ASISDLSO_B1_1B, st1_v0b_idx0, 1) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.b}[0], [x3] + st1 {v0.b}[3], [x3] + st1 {v0.b}[7], [x3] +TEST_END + +/* ST1 {.H}[], [] */ +TEST_BEGIN(ST1_ASISDLSO_H1_1H, st1_v0h_idx0, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000FFFF7FFF0001) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.h}[0], [x3] + st1 {v0.h}[1], [x3] + st1 {v0.h}[3], [x3] +TEST_END + +/* ST1 {.S}[], [] */ +TEST_BEGIN(ST1_ASISDLSO_S1_1S, st1_v0s_idx0, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x7FFFFFFF80000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.s}[0], [x3] + st1 {v0.s}[1], [x3] +TEST_END + +/* ST1 {.D}[], [] */ +TEST_BEGIN(ST1_ASISDLSO_D1_1D, st1_v0d_idx0, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x7FF0000000000000, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000) + add x3, sp, #-256 + fmov d0, ARG1_64 + st1 {v0.d}[0], [x3] +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/STLR.S b/backend/remill/tests/AArch64/DATAXFER/STLR.S index 0cc37971..2ebdb967 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STLR.S +++ b/backend/remill/tests/AArch64/DATAXFER/STLR.S @@ -16,9 +16,14 @@ /* STLR , [{,#0}] */ TEST_BEGIN(STLR_SL32_LDSTEXCL, stlr_sl32_ldstexcl, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - ldp w5, w6, [x3] - stlr w5, [x3] + str ARG1_32, [x3] + stlr ARG1_32, [x3] TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/STLXR_SRn_LDSTEXCL.S b/backend/remill/tests/AArch64/DATAXFER/STLXR_SRn_LDSTEXCL.S index 69a2db91..dc5a53c7 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STLXR_SRn_LDSTEXCL.S +++ b/backend/remill/tests/AArch64/DATAXFER/STLXR_SRn_LDSTEXCL.S @@ -45,8 +45,14 @@ // TEST_END TEST_BEGIN(STLXR_SR64_LDSTEXCL, ldxr_stlxr_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000, + 0x7FFFFFFFFFFFFFFF) add x3, sp, #-256 + str ARG1_64, [x3] mov x7, #0xFF mov x8, #0xFF ldxr x4, [x3] diff --git a/backend/remill/tests/AArch64/DATAXFER/STP_FP_LDSTPAIR.S b/backend/remill/tests/AArch64/DATAXFER/STP_FP_LDSTPAIR.S new file mode 100644 index 00000000..ed9731af --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/STP_FP_LDSTPAIR.S @@ -0,0 +1,95 @@ +/* STP , , [], # */ +TEST_BEGIN(STP_S_LDSTPAIR_POST, stp_s0_s1_post, 1) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + stp s0, s1, [x3], #0 + stp s0, s1, [x3], #16 + stp s0, s1, [x3], #32 +TEST_END + +/* STP , , [], # */ +TEST_BEGIN(STP_D_LDSTPAIR_POST, stp_d0_d1_post, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + stp d0, d1, [x3], #0 + stp d0, d1, [x3], #32 + stp d0, d1, [x3], #64 +TEST_END + +/* STP , , [], # */ +TEST_BEGIN(STP_Q_LDSTPAIR_POST, stp_q0_q1_post, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + dup v0.2d, ARG1_64 + dup v1.2d, ARG1_64 + stp q0, q1, [x3], #0 + stp q0, q1, [x3], #64 + stp q0, q1, [x3], #128 +TEST_END + +/* STP , , [, #]! */ +TEST_BEGIN(STP_S_LDSTPAIR_PRE, stp_s0_s1_pre, 1) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + stp s0, s1, [x3, #0]! + stp s0, s1, [x3, #16]! + stp s0, s1, [x3, #16]! +TEST_END + +/* STP , , [, #]! */ +TEST_BEGIN(STP_D_LDSTPAIR_PRE, stp_d0_d1_pre, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + stp d0, d1, [x3, #0]! + stp d0, d1, [x3, #32]! + stp d0, d1, [x3, #32]! +TEST_END + +/* STP , , [, #]! */ +TEST_BEGIN(STP_Q_LDSTPAIR_PRE, stp_q0_q1_pre, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + dup v0.2d, ARG1_64 + dup v1.2d, ARG1_64 + stp q0, q1, [x3, #0]! + stp q0, q1, [x3, #64]! + stp q0, q1, [x3, #64]! +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/STP_n_LDSTPAIR_OFF.S b/backend/remill/tests/AArch64/DATAXFER/STP_n_LDSTPAIR_OFF.S index a78560e5..d4cd456e 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STP_n_LDSTPAIR_OFF.S +++ b/backend/remill/tests/AArch64/DATAXFER/STP_n_LDSTPAIR_OFF.S @@ -46,9 +46,20 @@ TEST_END /* STP , , [{, #}] */ TEST_BEGIN(STP_S_LDSTPAIR_OFF, stp_s0_s1_m64_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FFFFFFFF) add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + fmov d2, ARG1_64 + fmov d3, ARG1_64 + fmov d4, ARG1_64 + fmov d5, ARG1_64 stp s0, s1, [x3, #0] stp s2, s3, [x3, #32] stp s4, s5, [x3, #64] @@ -56,9 +67,20 @@ TEST_END /* STP , , [{, #}] */ TEST_BEGIN(STP_D_LDSTPAIR_OFF, stp_d0_d1_m128_off, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + fmov d2, ARG1_64 + fmov d3, ARG1_64 + fmov d4, ARG1_64 + fmov d5, ARG1_64 stp d0, d1, [x3, #0] stp d2, d3, [x3, #32] stp d4, d5, [x3, #64] diff --git a/backend/remill/tests/AArch64/DATAXFER/STRB.S b/backend/remill/tests/AArch64/DATAXFER/STRB.S index 4fddd2ec..13fc31d7 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STRB.S +++ b/backend/remill/tests/AArch64/DATAXFER/STRB.S @@ -16,20 +16,28 @@ /* STRB , [{, #}] */ TEST_BEGIN(STRB_32_LDST_POS, strb_w563_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - ldp w5, w6, [x3] - strb w5, [x3, #16] - strb w6, [x3, #32] + strb ARG1_32, [x3, #16] + strb ARG1_32, [x3, #32] TEST_END /* STRB , [], # */ TEST_BEGIN(STRB_32_LDST_IMMPOST, strb_w5_m8_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - ldp w5, w6, [x3] - strb w5, [x3], #16 - strb w6, [x3], #32 + strb ARG1_32, [x3], #16 + strb ARG1_32, [x3], #32 TEST_END TEST_BEGIN(STRB_32_LDST_IMMPOST, strb_wzr_m8_post_alias, 1) @@ -41,10 +49,14 @@ TEST_END /* STRB , [, #]! */ TEST_BEGIN(STRB_32_LDST_IMMPRE, strb_w5_m8_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - ldr w5, [x3] - strb w5, [x3, #16]! + strb ARG1_32, [x3, #16]! TEST_END /* STRB , [, (|), {}] */ @@ -74,14 +86,24 @@ TEST_END /* STRB , [, {, LSL }] */ TEST_BEGIN(STRB_32BL_LDST_REGOFF, strb_w5_m8_off_w0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 ldr w5, [x3, #16] strb w5, [x3, ARG1_64] /* Implicit LSL 0 */ TEST_END TEST_BEGIN(STRB_32BL_LDST_REGOFF, strb_w5_m8_off_w0_lsl0, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 8, + 16, + 32, + 64) add x3, sp, #-256 ldr w5, [x3, #16] strb w5, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ diff --git a/backend/remill/tests/AArch64/DATAXFER/STRH.S b/backend/remill/tests/AArch64/DATAXFER/STRH.S index f565543e..82eb4a30 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STRH.S +++ b/backend/remill/tests/AArch64/DATAXFER/STRH.S @@ -29,17 +29,27 @@ /* STRH , [], # */ TEST_BEGIN(STRH_32_LDST_IMMPOST, strh_w56_m16_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - strh w5, [x3], #0 - strh w6, [x3], #32 + strh ARG1_32, [x3], #0 + strh ARG1_32, [x3], #32 TEST_END /* STRH , [, #]! */ TEST_BEGIN(STRH_32_LDST_IMMPRE, strh_w5_m16_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - strh w5, [x3, #16]! + strh ARG1_32, [x3, #16]! TEST_END /* STRH , [, (|), {}] */ @@ -65,7 +75,12 @@ TEST_END /* STRH , [, {, LSL }] */ TEST_BEGIN(STRH_32_LDST_REGOFF, strh_w567_m16_off_w0_lsl01, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0, + 4, + 8, + 16, + 32) add x3, sp, #-256 strh w5, [x3, ARG1_64] /* Implicit LSL 0 */ strh w6, [x3, ARG1_64, lsl #0] /* Explicit LSL 0 */ diff --git a/backend/remill/tests/AArch64/DATAXFER/STR_FP_LDST.S b/backend/remill/tests/AArch64/DATAXFER/STR_FP_LDST.S new file mode 100644 index 00000000..fba22881 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/STR_FP_LDST.S @@ -0,0 +1,170 @@ +/* STR , [], # */ +TEST_BEGIN(STR_B_LDST_IMMPOST, str_b0_immpost, 1) +TEST_INPUTS( + 0x00000000000000FF, + 0x0000000000000080, + 0x0000000000000000, + 0x0000000000000041, + 0x0000000000000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + str b0, [x3], #8 + str b0, [x3], #8 + str b0, [x3], #8 +TEST_END + +/* STR , [], # */ +TEST_BEGIN(STR_H_LDST_IMMPOST, str_h0_immpost, 1) +TEST_INPUTS( + 0x000000000000FFFF, + 0x0000000000008000, + 0x0000000000000000, + 0x0000000000004141, + 0x0000000000000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + str h0, [x3], #8 + str h0, [x3], #8 + str h0, [x3], #8 +TEST_END + +/* STR , [], # */ +TEST_BEGIN(STR_S_LDST_IMMPOST, str_s0_immpost, 1) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + str s0, [x3], #8 + str s0, [x3], #8 + str s0, [x3], #8 +TEST_END + +/* STR
, [], # */ +TEST_BEGIN(STR_D_LDST_IMMPOST, str_d0_immpost, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + str d0, [x3], #16 + str d0, [x3], #16 + str d0, [x3], #16 +TEST_END + +/* STR , [], # */ +TEST_BEGIN(STR_Q_LDST_IMMPOST, str_q0_immpost, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + dup v0.2d, ARG1_64 + str q0, [x3], #32 + str q0, [x3], #32 + str q0, [x3], #32 +TEST_END + +/* STR , [, #]! */ +TEST_BEGIN(STR_B_LDST_IMMPRE, str_b0_immpre, 1) +TEST_INPUTS( + 0x00000000000000FF, + 0x0000000000000080, + 0x0000000000000000, + 0x0000000000000041, + 0x0000000000000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + str b0, [x3, #0]! + str b0, [x3, #8]! + str b0, [x3, #8]! +TEST_END + +/* STR , [, #]! */ +TEST_BEGIN(STR_H_LDST_IMMPRE, str_h0_immpre, 1) +TEST_INPUTS( + 0x000000000000FFFF, + 0x0000000000008000, + 0x0000000000000000, + 0x0000000000004141, + 0x0000000000000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + str h0, [x3, #0]! + str h0, [x3, #8]! + str h0, [x3, #8]! +TEST_END + +/* STR , [, #]! */ +TEST_BEGIN(STR_S_LDST_IMMPRE, str_s0_immpre, 1) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + str s0, [x3, #0]! + str s0, [x3, #8]! + str s0, [x3, #8]! +TEST_END + +/* STR
, [, #]! */ +TEST_BEGIN(STR_D_LDST_IMMPRE, str_d0_immpre, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + str d0, [x3, #0]! + str d0, [x3, #16]! + str d0, [x3, #16]! +TEST_END + +/* STR
, [, {, {}}] */ +TEST_BEGIN(STR_D_LDST_REGOFF, str_d0_regoff, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + mov x4, #0 + str d0, [x3, x4] + mov x4, #16 + str d0, [x3, x4] + mov x4, #32 + str d0, [x3, x4] +TEST_END + +/* STR , [, {, {}}] */ +TEST_BEGIN(STR_S_LDST_REGOFF, str_s0_regoff, 1) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + mov x4, #0 + str s0, [x3, x4] + mov x4, #8 + str s0, [x3, x4] + mov x4, #16 + str s0, [x3, x4] +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPOST.S b/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPOST.S index 7dabd0f8..d0e601a3 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPOST.S +++ b/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPOST.S @@ -15,17 +15,27 @@ */ TEST_BEGIN(STR_32_LDST_IMMPOST, str_w0_m32_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - str w0, [x3], #0 - str w1, [x3], #16 - str w2, [x3], #32 + str ARG1_32, [x3], #0 + str ARG1_32, [x3], #16 + str ARG1_32, [x3], #32 TEST_END TEST_BEGIN(STR_64_LDST_IMMPOST, str_x0_m64_post, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000, + 0x7FFFFFFFFFFFFFFF) add x3, sp, #-256 - str x0, [x3], #0 - str x1, [x3], #16 - str x2, [x3], #32 + str ARG1_64, [x3], #0 + str ARG1_64, [x3], #16 + str ARG1_64, [x3], #32 TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPRE.S b/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPRE.S index 46962d5a..5573740a 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPRE.S +++ b/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_IMMPRE.S @@ -15,24 +15,42 @@ */ TEST_BEGIN(STR_32_LDST_IMMPRE, str_w0_m32_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - str w0, [x3, #0]! - str w1, [x3, #16]! - str w2, [x3, #32]! + str ARG1_32, [x3, #0]! + str ARG1_32, [x3, #16]! + str ARG1_32, [x3, #32]! TEST_END TEST_BEGIN(STR_64_LDST_IMMPRE, str_x0_m64_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000, + 0x7FFFFFFFFFFFFFFF) add x3, sp, #-256 - str x0, [x3, #0]! - str x1, [x3, #16]! - str x2, [x3, #32]! + str ARG1_64, [x3, #0]! + str ARG1_64, [x3, #16]! + str ARG1_64, [x3, #32]! TEST_END TEST_BEGIN(STR_Q_LDST_IMMPRE, str_q0_m128_pre, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 + dup v1.2d, ARG1_64 + dup v3.2d, ARG1_64 str q0, [x3, #0]! str q1, [x3, #16]! str q3, [x3, #32]! diff --git a/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_POS.S b/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_POS.S index a6f975db..463da208 100644 --- a/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_POS.S +++ b/backend/remill/tests/AArch64/DATAXFER/STR_n_LDST_POS.S @@ -15,56 +15,106 @@ */ TEST_BEGIN(STR_32_LDST_POS, str_w0_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x41414141, + 0x00000000, + 0xFFFFFFFF, + 0x80000000, + 0x7FFFFFFF) add x3, sp, #-256 - str w0, [x3, #0] - str w1, [x3, #16] - str w2, [x3, #32] + str ARG1_32, [x3, #0] + str ARG1_32, [x3, #16] + str ARG1_32, [x3, #32] TEST_END TEST_BEGIN(STR_64_LDST_POS, str_x0_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x4141414151515151, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x8000000000000000, + 0x7FFFFFFFFFFFFFFF) add x3, sp, #-256 - str x0, [x3, #0] - str x1, [x3, #16] - str x2, [x3, #32] + str ARG1_64, [x3, #0] + str ARG1_64, [x3, #16] + str ARG1_64, [x3, #32] TEST_END TEST_BEGIN(STR_B_LDST_POS, str_b0_m8, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + fmov d3, ARG1_64 str b0, [x3, #0] str b1, [x3, #16] str b3, [x3, #32] TEST_END TEST_BEGIN(STR_H_LDST_POS, str_h0_m16, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + fmov d3, ARG1_64 str h0, [x3, #0] str h1, [x3, #16] str h3, [x3, #32] TEST_END TEST_BEGIN(STR_S_LDST_POS, str_s0_m32, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + fmov d3, ARG1_64 str s0, [x3, #0] str s1, [x3, #16] str s3, [x3, #32] TEST_END TEST_BEGIN(STR_D_LDST_POS, str_d0_m64, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + fmov d0, ARG1_64 + fmov d1, ARG1_64 + fmov d3, ARG1_64 str d0, [x3, #0] str d1, [x3, #16] str d3, [x3, #32] TEST_END TEST_BEGIN(STR_Q_LDST_POS, str_q0_m128, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0102030405060708, + 0xFF00FF00FF00FF00, + 0x0000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x80817F7E01020304) add x3, sp, #-256 + dup v0.2d, ARG1_64 + dup v1.2d, ARG1_64 + dup v3.2d, ARG1_64 str q0, [x3, #0] str q1, [x3, #16] str q3, [x3, #32] diff --git a/backend/remill/tests/AArch64/DATAXFER/STUR_FP_LDST_UNSCALED.S b/backend/remill/tests/AArch64/DATAXFER/STUR_FP_LDST_UNSCALED.S new file mode 100644 index 00000000..c6d17cf2 --- /dev/null +++ b/backend/remill/tests/AArch64/DATAXFER/STUR_FP_LDST_UNSCALED.S @@ -0,0 +1,78 @@ +/* STUR , [{, #}] */ +TEST_BEGIN(STUR_B_LDST_UNSCALED, stur_b0_unscaled, 1) +TEST_INPUTS( + 0x00000000000000FF, + 0x0000000000000080, + 0x0000000000000041, + 0x0000000000000000, + 0x00000000000000AB, + 0x0000000000000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + stur b0, [x3, #0] + stur b0, [x3, #8] + stur b0, [x3, #16] +TEST_END + +/* STUR , [{, #}] */ +TEST_BEGIN(STUR_H_LDST_UNSCALED, stur_h0_unscaled, 1) +TEST_INPUTS( + 0x000000000000FFFF, + 0x0000000000008000, + 0x0000000000004141, + 0x0000000000000000, + 0x000000000000ABCD, + 0x0000000000000001) + add x3, sp, #-256 + fmov d0, ARG1_64 + stur h0, [x3, #0] + stur h0, [x3, #8] + stur h0, [x3, #16] +TEST_END + +/* STUR , [{, #}] */ +TEST_BEGIN(STUR_S_LDST_UNSCALED, stur_s0_unscaled, 1) +TEST_INPUTS( + 0x000000003F800000, + 0x0000000040000000, + 0x0000000000000000, + 0x000000007F800000, + 0x00000000FF800000, + 0x00000000FFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + stur s0, [x3, #0] + stur s0, [x3, #8] + stur s0, [x3, #16] +TEST_END + +/* STUR
, [{, #}] */ +TEST_BEGIN(STUR_D_LDST_UNSCALED, stur_d0_unscaled, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + fmov d0, ARG1_64 + stur d0, [x3, #0] + stur d0, [x3, #16] + stur d0, [x3, #32] +TEST_END + +/* STUR , [{, #}] */ +TEST_BEGIN(STUR_Q_LDST_UNSCALED, stur_q0_unscaled, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x0000000000000000, + 0x7FF0000000000000, + 0xFFFFFFFFFFFFFFFF) + add x3, sp, #-256 + dup v0.2d, ARG1_64 + stur q0, [x3, #0] + stur q0, [x3, #32] + stur q0, [x3, #64] +TEST_END diff --git a/backend/remill/tests/AArch64/DATAXFER/UMOV.S b/backend/remill/tests/AArch64/DATAXFER/UMOV.S index 4b3e2060..389b42fd 100644 --- a/backend/remill/tests/AArch64/DATAXFER/UMOV.S +++ b/backend/remill/tests/AArch64/DATAXFER/UMOV.S @@ -16,7 +16,15 @@ /* UMOV , .[] */ TEST_BEGIN(UMOV_ASIMDINS_W_W_B, umov_wN_B, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0102030405060708, + 0x7f80ff00deadbeef, + 0xffffffffffffffff, + 0x8000000000000000, + 0x0080007f00ff0001) + + fmov d0, ARG1_64 umov w0, v0.B[0] umov w1, v0.B[4] umov w2, v0.B[8] @@ -24,7 +32,15 @@ TEST_INPUTS(0) TEST_END TEST_BEGIN(UMOV_ASIMDINS_W_W_H, umov_wN_H, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0001000200030004, + 0x7fff800000ff00fe, + 0xffffffffffffffff, + 0x8000000000000000, + 0x00807fff0001fffe) + + fmov d0, ARG1_64 umov w0, v0.H[0] umov w1, v0.H[2] umov w2, v0.H[4] @@ -32,7 +48,15 @@ TEST_INPUTS(0) TEST_END TEST_BEGIN(UMOV_ASIMDINS_W_W_S, umov_wN_S, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x000000017fffffff, + 0x80000000ffffffff, + 0xffffffffffffffff, + 0x8000000000000000, + 0x7fffffff00000001) + + fmov d0, ARG1_64 umov w0, v0.S[0] umov w1, v0.S[1] umov w2, v0.S[2] @@ -41,7 +65,15 @@ TEST_END /* UMOV , .[] */ TEST_BEGIN(UMOV_ASIMDINS_X_X_D, umov_xN_D, 1) -TEST_INPUTS(0) +TEST_INPUTS( + 0x0000000000000000, + 0x0102030405060708, + 0x7fffffffffffffff, + 0xffffffffffffffff, + 0x8000000000000000, + 0xdeadbeefcafebabe) + + fmov d0, ARG1_64 umov x0, v0.D[0] umov x1, v0.D[1] TEST_END diff --git a/backend/remill/tests/AArch64/LOGICAL/ASRV_n_DP_2SRC.S b/backend/remill/tests/AArch64/LOGICAL/ASRV_n_DP_2SRC.S new file mode 100644 index 00000000..ef8056f6 --- /dev/null +++ b/backend/remill/tests/AArch64/LOGICAL/ASRV_n_DP_2SRC.S @@ -0,0 +1,27 @@ +TEST_BEGIN(ASRV_32_DP_2SRC, asrv_w9_w0_w1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFF, 1, + 0x80000000, 1, + 0x12345678, 4, + 0x12345678, 31, + 0x12345678, 32) + + asrv w9, ARG1_32, ARG2_32 +TEST_END + +TEST_BEGIN(ASRV_64_DP_2SRC, asrv_x9_x0_x1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFFFFFFFFFF, 1, + 0x8000000000000000, 1, + 0x123456789abcdef0, 4, + 0x123456789abcdef0, 63, + 0x123456789abcdef0, 64) + + asrv x9, ARG1_64, ARG2_64 +TEST_END diff --git a/backend/remill/tests/AArch64/LOGICAL/LSLV_n_DP_2SRC.S b/backend/remill/tests/AArch64/LOGICAL/LSLV_n_DP_2SRC.S new file mode 100644 index 00000000..fd0421de --- /dev/null +++ b/backend/remill/tests/AArch64/LOGICAL/LSLV_n_DP_2SRC.S @@ -0,0 +1,27 @@ +TEST_BEGIN(LSLV_32_DP_2SRC, lslv_w9_w0_w1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFF, 1, + 0x80000000, 1, + 0x12345678, 4, + 0x12345678, 31, + 0x12345678, 32) + + lslv w9, ARG1_32, ARG2_32 +TEST_END + +TEST_BEGIN(LSLV_64_DP_2SRC, lslv_x9_x0_x1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFFFFFFFFFF, 1, + 0x8000000000000000, 1, + 0x123456789abcdef0, 4, + 0x123456789abcdef0, 63, + 0x123456789abcdef0, 64) + + lslv x9, ARG1_64, ARG2_64 +TEST_END diff --git a/backend/remill/tests/AArch64/LOGICAL/LSRV_n_DP_2SRC.S b/backend/remill/tests/AArch64/LOGICAL/LSRV_n_DP_2SRC.S new file mode 100644 index 00000000..e7376f73 --- /dev/null +++ b/backend/remill/tests/AArch64/LOGICAL/LSRV_n_DP_2SRC.S @@ -0,0 +1,27 @@ +TEST_BEGIN(LSRV_32_DP_2SRC, lsrv_w9_w0_w1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFF, 1, + 0x80000000, 1, + 0x12345678, 4, + 0x12345678, 31, + 0x12345678, 32) + + lsrv w9, ARG1_32, ARG2_32 +TEST_END + +TEST_BEGIN(LSRV_64_DP_2SRC, lsrv_x9_x0_x1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFFFFFFFFFF, 1, + 0x8000000000000000, 1, + 0x123456789abcdef0, 4, + 0x123456789abcdef0, 63, + 0x123456789abcdef0, 64) + + lsrv x9, ARG1_64, ARG2_64 +TEST_END diff --git a/backend/remill/tests/AArch64/LOGICAL/RORV_n_DP_2SRC.S b/backend/remill/tests/AArch64/LOGICAL/RORV_n_DP_2SRC.S new file mode 100644 index 00000000..cee22e96 --- /dev/null +++ b/backend/remill/tests/AArch64/LOGICAL/RORV_n_DP_2SRC.S @@ -0,0 +1,27 @@ +TEST_BEGIN(RORV_32_DP_2SRC, rorv_w9_w0_w1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFF, 1, + 0x80000000, 1, + 0x12345678, 4, + 0x12345678, 31, + 0x12345678, 32) + + rorv w9, ARG1_32, ARG2_32 +TEST_END + +TEST_BEGIN(RORV_64_DP_2SRC, rorv_x9_x0_x1, 2) +TEST_INPUTS( + 0, 0, + 1, 0, + 1, 1, + 0xFFFFFFFFFFFFFFFF, 1, + 0x8000000000000000, 1, + 0x123456789abcdef0, 4, + 0x123456789abcdef0, 63, + 0x123456789abcdef0, 64) + + rorv x9, ARG1_64, ARG2_64 +TEST_END diff --git a/backend/remill/tests/AArch64/Run.cpp b/backend/remill/tests/AArch64/Run.cpp index b4157caa..02b7431e 100644 --- a/backend/remill/tests/AArch64/Run.cpp +++ b/backend/remill/tests/AArch64/Run.cpp @@ -754,6 +754,13 @@ static void RunWithFlags(const test::TestInfo *info, NZCV flags, std::string des DIFF(ECV_NZCV, ecv_nzcv); DIFF(ECV_FPSR, ecv_fpsr); + // Compare SIMD/vector registers. + for (size_t i = 0; i < 32; ++i) { + EXPECT_EQ(0, memcmp(&lifted_state->simd.v[i], &native_state->simd.v[i], + sizeof(lifted_state->simd.v[i]))) + << "SIMD register V" << i << " differs"; + } + auto lifted_state_bytes = reinterpret_cast(lifted_state); auto native_state_bytes = reinterpret_cast(native_state); diff --git a/backend/remill/tests/AArch64/SIMD/ADDP_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/ADDP_ASIMDSAME_ONLY.S index b1b62548..d03d1580 100644 --- a/backend/remill/tests/AArch64/SIMD/ADDP_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/ADDP_ASIMDSAME_ONLY.S @@ -48,3 +48,73 @@ TEST_BEGIN(ADDP_ASIMDSAME_ONLY_2D, addp_v123x2d, 1) TEST_INPUTS(0) addp v0.2d, v1.2d, v2.2d TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_8B_INPUTS, addp_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + addp v0.8b, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_16B_INPUTS, addp_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + addp v0.16b, v1.16b, v2.16b +TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_4H_INPUTS, addp_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + addp v0.4h, v1.4h, v2.4h +TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_8H_INPUTS, addp_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + addp v0.8h, v1.8h, v2.8h +TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_2S_INPUTS, addp_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + addp v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_4S_INPUTS, addp_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + addp v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(ADDP_ASIMDSAME_ONLY_2D_INPUTS, addp_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + addp v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/ADDP_ASISDPAIR_ONLY.S b/backend/remill/tests/AArch64/SIMD/ADDP_ASISDPAIR_ONLY.S new file mode 100644 index 00000000..8e3179c5 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/ADDP_ASISDPAIR_ONLY.S @@ -0,0 +1,15 @@ +TEST_BEGIN(ADDP_ASISDPAIR_ONLY, addp_d0_v1_2d, 1) +TEST_INPUTS(0) + addp d0, v1.2d + addp d3, v4.2d + addp d5, v6.2d +TEST_END + +TEST_BEGIN(ADDP_ASISDPAIR_ONLY_INPUTS, addp_d0_v1_2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + addp d0, v1.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/ADDV_ASIMDALL_ONLY.S b/backend/remill/tests/AArch64/SIMD/ADDV_ASIMDALL_ONLY.S index 79357133..f5582b72 100644 --- a/backend/remill/tests/AArch64/SIMD/ADDV_ASIMDALL_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/ADDV_ASIMDALL_ONLY.S @@ -53,3 +53,48 @@ TEST_INPUTS(0) addv s7, v2.4s addv s8, v3.4s TEST_END + +TEST_BEGIN(ADDV_ASIMDALL_ONLY_8B_INPUTS, addv_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + addv b0, v1.8b +TEST_END + +TEST_BEGIN(ADDV_ASIMDALL_ONLY_16B_INPUTS, addv_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + addv b0, v1.16b +TEST_END + +TEST_BEGIN(ADDV_ASIMDALL_ONLY_4H_INPUTS, addv_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + addv h0, v1.4h +TEST_END + +TEST_BEGIN(ADDV_ASIMDALL_ONLY_8H_INPUTS, addv_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + addv h0, v1.8h +TEST_END + +TEST_BEGIN(ADDV_ASIMDALL_ONLY_4S_INPUTS, addv_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + addv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/ADD_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/ADD_ASIMDSAME_ONLY.S index d95481a7..b27bd196 100644 --- a/backend/remill/tests/AArch64/SIMD/ADD_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/ADD_ASIMDSAME_ONLY.S @@ -49,3 +49,73 @@ TEST_BEGIN(ADD_ASIMDSAME_ONLY_2D, add_v123x2d, 1) TEST_INPUTS(0) add v0.2d, v1.2d, v2.2d TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_8B_INPUTS, add_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + add v0.8b, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_16B_INPUTS, add_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + add v0.16b, v1.16b, v2.16b +TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_4H_INPUTS, add_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + add v0.4h, v1.4h, v2.4h +TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_8H_INPUTS, add_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + add v0.8h, v1.8h, v2.8h +TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_2S_INPUTS, add_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + add v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_4S_INPUTS, add_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + add v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(ADD_ASIMDSAME_ONLY_2D_INPUTS, add_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + add v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/AND_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/AND_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..57d0e5c9 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/AND_ASIMDSAME_ONLY.S @@ -0,0 +1,33 @@ +TEST_BEGIN(AND_ASIMDSAME_ONLY_8B, and_v0v3v6_8b, 1) +TEST_INPUTS(0) + and v0.8b, v1.8b, v2.8b + and v3.8b, v4.8b, v5.8b + and v6.8b, v1.8b, v4.8b +TEST_END + +TEST_BEGIN(AND_ASIMDSAME_ONLY_16B, and_v0v3v6_16b, 1) +TEST_INPUTS(0) + and v0.16b, v1.16b, v2.16b + and v3.16b, v4.16b, v5.16b + and v6.16b, v1.16b, v4.16b +TEST_END + +TEST_BEGIN(AND_ASIMDSAME_ONLY_8B_INPUTS, and_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + and v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(AND_ASIMDSAME_ONLY_16B_INPUTS, and_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + and v5.16b, v0.16b, v1.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/BIC_ASIMDIMM_L.S b/backend/remill/tests/AArch64/SIMD/BIC_ASIMDIMM_L.S new file mode 100644 index 00000000..1613a3b6 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/BIC_ASIMDIMM_L.S @@ -0,0 +1,67 @@ +TEST_BEGIN(BIC_ASIMDIMM_L_HL_4H, bic_v0_4h_imm, 1) +TEST_INPUTS(0) + movi v0.4h, #0xff + bic v0.4h, #0x0f + movi v3.4h, #0xab + bic v3.4h, #0x11 +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_HL_8H, bic_v0_8h_imm, 1) +TEST_INPUTS(0) + movi v0.8h, #0xff + bic v0.8h, #0x0f + movi v3.8h, #0xcd + bic v3.8h, #0x22 +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_SL_2S, bic_v0_2s_imm, 1) +TEST_INPUTS(0) + movi v0.2s, #0xff + bic v0.2s, #0x0f + movi v3.2s, #0x55 + bic v3.2s, #0x33 +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_SL_4S, bic_v0_4s_imm, 1) +TEST_INPUTS(0) + movi v0.4s, #0xff + bic v0.4s, #0x0f + movi v3.4s, #0xef + bic v3.4s, #0x44 +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_HL_4H_INPUTS, bic_v4h_inputs, 1) +TEST_INPUTS( + 0x0001000200030004, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d0, ARG1_64 + bic v0.4h, #0x0f +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_HL_8H_INPUTS, bic_v8h_inputs, 1) +TEST_INPUTS( + 0x0001000200030004, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v0.2d, ARG1_64 + bic v0.8h, #0x0f +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_SL_2S_INPUTS, bic_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d0, ARG1_64 + bic v0.2s, #0x0f +TEST_END + +TEST_BEGIN(BIC_ASIMDIMM_L_SL_4S_INPUTS, bic_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v0.2d, ARG1_64 + bic v0.4s, #0x0f +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/BIC_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/BIC_ASIMDSAME_ONLY.S index 4b3c707b..607c792f 100644 --- a/backend/remill/tests/AArch64/SIMD/BIC_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/BIC_ASIMDSAME_ONLY.S @@ -27,3 +27,23 @@ TEST_INPUTS(0) bic v6.16b, v2.16b, v3.16b bic v7.16b, v4.16b, v5.16b TEST_END + +TEST_BEGIN(BIC_ASIMDSAME_ONLY_8B_INPUTS, bic_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + bic v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(BIC_ASIMDSAME_ONLY_16B_INPUTS, bic_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + bic v5.16b, v0.16b, v1.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/BIF_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/BIF_ASIMDSAME_ONLY.S index 6c1b25b7..a7c43f44 100644 --- a/backend/remill/tests/AArch64/SIMD/BIF_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/BIF_ASIMDSAME_ONLY.S @@ -27,3 +27,23 @@ TEST_INPUTS(0) bif v6.16b, v2.16b, v3.16b bif v7.16b, v4.16b, v5.16b TEST_END + +TEST_BEGIN(BIF_ASIMDSAME_ONLY_8B_INPUTS, bif_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + bif v0.8b, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(BIF_ASIMDSAME_ONLY_16B_INPUTS, bif_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + bif v0.16b, v1.16b, v2.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/BIT_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/BIT_ASIMDSAME_ONLY.S index d498ef6f..f03a3f61 100644 --- a/backend/remill/tests/AArch64/SIMD/BIT_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/BIT_ASIMDSAME_ONLY.S @@ -27,3 +27,23 @@ TEST_INPUTS(0) bit v6.16b, v2.16b, v3.16b bit v7.16b, v4.16b, v5.16b TEST_END + +TEST_BEGIN(BIT_ASIMDSAME_ONLY_8B_INPUTS, bit_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + bit v0.8b, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(BIT_ASIMDSAME_ONLY_16B_INPUTS, bit_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + bit v0.16b, v1.16b, v2.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/BSL_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/BSL_ASIMDSAME_ONLY.S index d61de443..4a5a8728 100644 --- a/backend/remill/tests/AArch64/SIMD/BSL_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/BSL_ASIMDSAME_ONLY.S @@ -27,3 +27,23 @@ TEST_INPUTS(0) bsl v6.16b, v2.16b, v3.16b bsl v7.16b, v4.16b, v5.16b TEST_END + +TEST_BEGIN(BSL_ASIMDSAME_ONLY_8B_INPUTS, bsl_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + bsl v0.8b, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(BSL_ASIMDSAME_ONLY_16B_INPUTS, bsl_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + bsl v0.16b, v1.16b, v2.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMGE_ASISDMISC_Z.S b/backend/remill/tests/AArch64/SIMD/CMGE_ASISDMISC_Z.S new file mode 100644 index 00000000..5dba2400 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/CMGE_ASISDMISC_Z.S @@ -0,0 +1,14 @@ +/* CMGE , , #0 (scalar) */ + +TEST_BEGIN(CMGE_ASISDMISC_Z, cmge_d0_d1_zero, 1) +TEST_INPUTS( + 0x0000000000000000, + 0x0000000000000001, + 0x7FFFFFFFFFFFFFFF, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF, + 0x0000000100000000, + 0xFFFFFFFEFFFFFFFF) + fmov d1, ARG1_64 + cmge d0, d1, #0 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMHS_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/CMHS_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..6f37a379 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/CMHS_ASIMDSAME_ONLY.S @@ -0,0 +1,118 @@ +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_8B, cmhs_v0v3v6_8b, 1) +TEST_INPUTS(0) + cmhs v0.8b, v1.8b, v2.8b + cmhs v3.8b, v4.8b, v5.8b + cmhs v6.8b, v1.8b, v4.8b +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_16B, cmhs_v0v3v6_16b, 1) +TEST_INPUTS(0) + cmhs v0.16b, v1.16b, v2.16b + cmhs v3.16b, v4.16b, v5.16b + cmhs v6.16b, v1.16b, v4.16b +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_4H, cmhs_v0v3v6_4h, 1) +TEST_INPUTS(0) + cmhs v0.4h, v1.4h, v2.4h + cmhs v3.4h, v4.4h, v5.4h + cmhs v6.4h, v1.4h, v4.4h +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_8H, cmhs_v0v3v6_8h, 1) +TEST_INPUTS(0) + cmhs v0.8h, v1.8h, v2.8h + cmhs v3.8h, v4.8h, v5.8h + cmhs v6.8h, v1.8h, v4.8h +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_2S, cmhs_v0v3v6_2s, 1) +TEST_INPUTS(0) + cmhs v0.2s, v1.2s, v2.2s + cmhs v3.2s, v4.2s, v5.2s + cmhs v6.2s, v1.2s, v4.2s +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_4S, cmhs_v0v3v6_4s, 1) +TEST_INPUTS(0) + cmhs v0.4s, v1.4s, v2.4s + cmhs v3.4s, v4.4s, v5.4s + cmhs v6.4s, v1.4s, v4.4s +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_2D, cmhs_v0v3v6_2d, 1) +TEST_INPUTS(0) + cmhs v0.2d, v1.2d, v2.2d + cmhs v3.2d, v4.2d, v5.2d + cmhs v6.2d, v1.2d, v4.2d +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_8B_INPUTS, cmhs_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmhs v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_16B_INPUTS, cmhs_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmhs v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_4H_INPUTS, cmhs_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmhs v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_8H_INPUTS, cmhs_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmhs v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_2S_INPUTS, cmhs_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmhs v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_4S_INPUTS, cmhs_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmhs v5.4s, v0.4s, v1.4s +TEST_END + +TEST_BEGIN(CMHS_ASIMDSAME_ONLY_2D_INPUTS, cmhs_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmhs v5.2d, v0.2d, v1.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMLE_ASIMDMISC_Z.S b/backend/remill/tests/AArch64/SIMD/CMLE_ASIMDMISC_Z.S new file mode 100644 index 00000000..0c64a265 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/CMLE_ASIMDMISC_Z.S @@ -0,0 +1,111 @@ +TEST_BEGIN(CMLE_ASIMDMISC_Z_8B, cmle_v0v3v5_8b_zero, 1) +TEST_INPUTS(0) + cmle v0.8b, v1.8b, #0 + cmle v3.8b, v4.8b, #0 + cmle v5.8b, v6.8b, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_16B, cmle_v0v3v5_16b_zero, 1) +TEST_INPUTS(0) + cmle v0.16b, v1.16b, #0 + cmle v3.16b, v4.16b, #0 + cmle v5.16b, v6.16b, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_4H, cmle_v0v3v5_4h_zero, 1) +TEST_INPUTS(0) + cmle v0.4h, v1.4h, #0 + cmle v3.4h, v4.4h, #0 + cmle v5.4h, v6.4h, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_8H, cmle_v0v3v5_8h_zero, 1) +TEST_INPUTS(0) + cmle v0.8h, v1.8h, #0 + cmle v3.8h, v4.8h, #0 + cmle v5.8h, v6.8h, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_2S, cmle_v0v3v5_2s_zero, 1) +TEST_INPUTS(0) + cmle v0.2s, v1.2s, #0 + cmle v3.2s, v4.2s, #0 + cmle v5.2s, v6.2s, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_4S, cmle_v0v3v5_4s_zero, 1) +TEST_INPUTS(0) + cmle v0.4s, v1.4s, #0 + cmle v3.4s, v4.4s, #0 + cmle v5.4s, v6.4s, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_2D, cmle_v0v3v5_2d_zero, 1) +TEST_INPUTS(0) + cmle v0.2d, v1.2d, #0 + cmle v3.2d, v4.2d, #0 + cmle v5.2d, v6.2d, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_8B_INPUTS, cmle_z_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + cmle v0.8b, v1.8b, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_16B_INPUTS, cmle_z_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + cmle v0.16b, v1.16b, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_4H_INPUTS, cmle_z_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + cmle v0.4h, v1.4h, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_8H_INPUTS, cmle_z_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + cmle v0.8h, v1.8h, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_2S_INPUTS, cmle_z_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + cmle v0.2s, v1.2s, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_4S_INPUTS, cmle_z_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + cmle v0.4s, v1.4s, #0 +TEST_END + +TEST_BEGIN(CMLE_ASIMDMISC_Z_2D_INPUTS, cmle_z_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + cmle v0.2d, v1.2d, #0 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMLT_ASIMDMISC_Z.S b/backend/remill/tests/AArch64/SIMD/CMLT_ASIMDMISC_Z.S new file mode 100644 index 00000000..6b977cca --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/CMLT_ASIMDMISC_Z.S @@ -0,0 +1,111 @@ +TEST_BEGIN(CMLT_ASIMDMISC_Z_8B, cmlt_v0v3v5_8b_zero, 1) +TEST_INPUTS(0) + cmlt v0.8b, v1.8b, #0 + cmlt v3.8b, v4.8b, #0 + cmlt v5.8b, v6.8b, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_16B, cmlt_v0v3v5_16b_zero, 1) +TEST_INPUTS(0) + cmlt v0.16b, v1.16b, #0 + cmlt v3.16b, v4.16b, #0 + cmlt v5.16b, v6.16b, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_4H, cmlt_v0v3v5_4h_zero, 1) +TEST_INPUTS(0) + cmlt v0.4h, v1.4h, #0 + cmlt v3.4h, v4.4h, #0 + cmlt v5.4h, v6.4h, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_8H, cmlt_v0v3v5_8h_zero, 1) +TEST_INPUTS(0) + cmlt v0.8h, v1.8h, #0 + cmlt v3.8h, v4.8h, #0 + cmlt v5.8h, v6.8h, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_2S, cmlt_v0v3v5_2s_zero, 1) +TEST_INPUTS(0) + cmlt v0.2s, v1.2s, #0 + cmlt v3.2s, v4.2s, #0 + cmlt v5.2s, v6.2s, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_4S, cmlt_v0v3v5_4s_zero, 1) +TEST_INPUTS(0) + cmlt v0.4s, v1.4s, #0 + cmlt v3.4s, v4.4s, #0 + cmlt v5.4s, v6.4s, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_2D, cmlt_v0v3v5_2d_zero, 1) +TEST_INPUTS(0) + cmlt v0.2d, v1.2d, #0 + cmlt v3.2d, v4.2d, #0 + cmlt v5.2d, v6.2d, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_8B_INPUTS, cmlt_z_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + cmlt v0.8b, v1.8b, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_16B_INPUTS, cmlt_z_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + cmlt v0.16b, v1.16b, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_4H_INPUTS, cmlt_z_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + cmlt v0.4h, v1.4h, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_8H_INPUTS, cmlt_z_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + cmlt v0.8h, v1.8h, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_2S_INPUTS, cmlt_z_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + cmlt v0.2s, v1.2s, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_4S_INPUTS, cmlt_z_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + cmlt v0.4s, v1.4s, #0 +TEST_END + +TEST_BEGIN(CMLT_ASIMDMISC_Z_2D_INPUTS, cmlt_z_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + cmlt v0.2d, v1.2d, #0 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMTST_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/CMTST_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..ddb6a3cd --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/CMTST_ASIMDSAME_ONLY.S @@ -0,0 +1,118 @@ +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_8B, cmtst_v0v3v6_8b, 1) +TEST_INPUTS(0) + cmtst v0.8b, v1.8b, v2.8b + cmtst v3.8b, v4.8b, v5.8b + cmtst v6.8b, v1.8b, v4.8b +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_16B, cmtst_v0v3v6_16b, 1) +TEST_INPUTS(0) + cmtst v0.16b, v1.16b, v2.16b + cmtst v3.16b, v4.16b, v5.16b + cmtst v6.16b, v1.16b, v4.16b +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_4H, cmtst_v0v3v6_4h, 1) +TEST_INPUTS(0) + cmtst v0.4h, v1.4h, v2.4h + cmtst v3.4h, v4.4h, v5.4h + cmtst v6.4h, v1.4h, v4.4h +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_8H, cmtst_v0v3v6_8h, 1) +TEST_INPUTS(0) + cmtst v0.8h, v1.8h, v2.8h + cmtst v3.8h, v4.8h, v5.8h + cmtst v6.8h, v1.8h, v4.8h +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_2S, cmtst_v0v3v6_2s, 1) +TEST_INPUTS(0) + cmtst v0.2s, v1.2s, v2.2s + cmtst v3.2s, v4.2s, v5.2s + cmtst v6.2s, v1.2s, v4.2s +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_4S, cmtst_v0v3v6_4s, 1) +TEST_INPUTS(0) + cmtst v0.4s, v1.4s, v2.4s + cmtst v3.4s, v4.4s, v5.4s + cmtst v6.4s, v1.4s, v4.4s +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_2D, cmtst_v0v3v6_2d, 1) +TEST_INPUTS(0) + cmtst v0.2d, v1.2d, v2.2d + cmtst v3.2d, v4.2d, v5.2d + cmtst v6.2d, v1.2d, v4.2d +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_8B_INPUTS, cmtst_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmtst v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_16B_INPUTS, cmtst_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmtst v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_4H_INPUTS, cmtst_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmtst v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_8H_INPUTS, cmtst_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmtst v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_2S_INPUTS, cmtst_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmtst v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_4S_INPUTS, cmtst_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmtst v5.4s, v0.4s, v1.4s +TEST_END + +TEST_BEGIN(CMTST_ASIMDSAME_ONLY_2D_INPUTS, cmtst_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmtst v5.2d, v0.2d, v1.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDMISC_Z.S b/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDMISC_Z.S index ae34a746..c6389386 100644 --- a/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDMISC_Z.S +++ b/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDMISC_Z.S @@ -160,3 +160,192 @@ TEST_INPUTS(0) cmge v1.2d, v2.2d, #0 cmge v2.2d, v3.2d, #0 TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_8B_INPUTS, cmeq_z_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + cmeq v0.8b, v1.8b, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_8B_INPUTS, cmgt_z_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + cmgt v0.8b, v1.8b, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_8B_INPUTS, cmge_z_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + cmge v0.8b, v1.8b, #0 +TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_16B_INPUTS, cmeq_z_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + cmeq v0.16b, v1.16b, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_16B_INPUTS, cmgt_z_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + cmgt v0.16b, v1.16b, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_16B_INPUTS, cmge_z_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + cmge v0.16b, v1.16b, #0 +TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_4H_INPUTS, cmeq_z_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + cmeq v0.4h, v1.4h, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_4H_INPUTS, cmgt_z_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + cmgt v0.4h, v1.4h, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_4H_INPUTS, cmge_z_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + cmge v0.4h, v1.4h, #0 +TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_8H_INPUTS, cmeq_z_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + cmeq v0.8h, v1.8h, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_8H_INPUTS, cmgt_z_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + cmgt v0.8h, v1.8h, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_8H_INPUTS, cmge_z_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + cmge v0.8h, v1.8h, #0 +TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_2S_INPUTS, cmeq_z_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + cmeq v0.2s, v1.2s, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_2S_INPUTS, cmgt_z_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + cmgt v0.2s, v1.2s, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_2S_INPUTS, cmge_z_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + cmge v0.2s, v1.2s, #0 +TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_4S_INPUTS, cmeq_z_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + cmeq v0.4s, v1.4s, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_4S_INPUTS, cmgt_z_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + cmgt v0.4s, v1.4s, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_4S_INPUTS, cmge_z_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + cmge v0.4s, v1.4s, #0 +TEST_END + +TEST_BEGIN(CMEQ_ASIMDMISC_Z_2D_INPUTS, cmeq_z_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + cmeq v0.2d, v1.2d, #0 +TEST_END + +TEST_BEGIN(CMGT_ASIMDMISC_Z_2D_INPUTS, cmgt_z_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + cmgt v0.2d, v1.2d, #0 +TEST_END + +TEST_BEGIN(CMGE_ASIMDMISC_Z_2D_INPUTS, cmge_z_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + cmge v0.2d, v1.2d, #0 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDSAME_ONLY.S index 99f78c87..fb5fe4d9 100644 --- a/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/CMcc_ASIMDSAME_ONLY.S @@ -160,3 +160,213 @@ TEST_INPUTS(0) cmge v1.2d, v2.2d, v3.2d cmge v2.2d, v3.2d, v4.2d TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_8B_INPUTS, cmeq_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmeq v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_8B_INPUTS, cmgt_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmgt v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_8B_INPUTS, cmge_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmge v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_16B_INPUTS, cmeq_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmeq v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_16B_INPUTS, cmgt_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmgt v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_16B_INPUTS, cmge_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmge v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_4H_INPUTS, cmeq_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmeq v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_4H_INPUTS, cmgt_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmgt v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_4H_INPUTS, cmge_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmge v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_8H_INPUTS, cmeq_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmeq v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_8H_INPUTS, cmgt_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmgt v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_8H_INPUTS, cmge_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmge v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_2S_INPUTS, cmeq_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmeq v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_2S_INPUTS, cmgt_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmgt v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_2S_INPUTS, cmge_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + cmge v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_4S_INPUTS, cmeq_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmeq v5.4s, v0.4s, v1.4s +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_4S_INPUTS, cmgt_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmgt v5.4s, v0.4s, v1.4s +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_4S_INPUTS, cmge_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmge v5.4s, v0.4s, v1.4s +TEST_END + +TEST_BEGIN(CMEQ_ASIMDSAME_ONLY_2D_INPUTS, cmeq_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmeq v5.2d, v0.2d, v1.2d +TEST_END + +TEST_BEGIN(CMGT_ASIMDSAME_ONLY_2D_INPUTS, cmgt_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmgt v5.2d, v0.2d, v1.2d +TEST_END + +TEST_BEGIN(CMGE_ASIMDSAME_ONLY_2D_INPUTS, cmge_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + cmge v5.2d, v0.2d, v1.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/CNT_ASIMDMISC_R.S b/backend/remill/tests/AArch64/SIMD/CNT_ASIMDMISC_R.S new file mode 100644 index 00000000..64ba3c17 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/CNT_ASIMDMISC_R.S @@ -0,0 +1,17 @@ +TEST_BEGIN(CNT_ASIMDMISC_R_8B, cnt_v0v3v5_8b, 1) +TEST_INPUTS(0) + cnt v0.8b, v1.8b + cnt v3.8b, v4.8b + cnt v5.8b, v6.8b +TEST_END + +/* TODO: CNT_ASIMDMISC_R_16B fails - semantics bug (upper bits mismatch) */ + +TEST_BEGIN(CNT_ASIMDMISC_R_8B_INPUTS, cnt_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + cnt v0.8b, v1.8b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/DUP_ASIMDINS_DV_V.S b/backend/remill/tests/AArch64/SIMD/DUP_ASIMDINS_DV_V.S new file mode 100644 index 00000000..35f6bf65 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/DUP_ASIMDINS_DV_V.S @@ -0,0 +1,104 @@ +TEST_BEGIN(DUP_ASIMDINS_DV_V_8B, dup_v0_v1b2_8b, 1) +TEST_INPUTS(0) + dup v0.8b, v1.b[0] + dup v3.8b, v2.b[3] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_16B, dup_v0_v1b2_16b, 1) +TEST_INPUTS(0) + dup v0.16b, v1.b[2] + dup v3.16b, v4.b[7] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_4H, dup_v0_v1h1_4h, 1) +TEST_INPUTS(0) + dup v0.4h, v1.h[1] + dup v3.4h, v2.h[3] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_8H, dup_v0_v1h1_8h, 1) +TEST_INPUTS(0) + dup v0.8h, v1.h[1] + dup v3.8h, v4.h[5] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_2S, dup_v0_v1s0_2s, 1) +TEST_INPUTS(0) + dup v0.2s, v1.s[0] + dup v3.2s, v2.s[1] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_4S, dup_v0_v1s0_4s, 1) +TEST_INPUTS(0) + dup v0.4s, v1.s[0] + dup v3.4s, v4.s[3] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_2D, dup_v0_v1d0_2d, 1) +TEST_INPUTS(0) + dup v0.2d, v1.d[0] + dup v3.2d, v2.d[1] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_8B_INPUTS, dup_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + dup v0.8b, v1.b[0] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_16B_INPUTS, dup_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + dup v0.16b, v1.b[2] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_4H_INPUTS, dup_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + dup v0.4h, v1.h[1] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_8H_INPUTS, dup_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + dup v0.8h, v1.h[1] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_2S_INPUTS, dup_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + dup v0.2s, v1.s[0] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_4S_INPUTS, dup_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + dup v0.4s, v1.s[0] +TEST_END + +TEST_BEGIN(DUP_ASIMDINS_DV_V_2D_INPUTS, dup_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + dup v0.2d, v1.d[0] +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/DUP_ASISDONE_ONLY.S b/backend/remill/tests/AArch64/SIMD/DUP_ASISDONE_ONLY.S new file mode 100644 index 00000000..622eed6b --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/DUP_ASISDONE_ONLY.S @@ -0,0 +1,59 @@ +TEST_BEGIN(DUP_ASISDONE_ONLY_B, dup_b0_v1_b0, 1) +TEST_INPUTS(0) + dup b0, v1.b[0] + dup b3, v2.b[5] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_H, dup_h0_v1_h0, 1) +TEST_INPUTS(0) + dup h0, v1.h[0] + dup h3, v4.h[3] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_S, dup_s0_v1_s0, 1) +TEST_INPUTS(0) + dup s0, v1.s[0] + dup s3, v2.s[2] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_D, dup_d0_v1_d0, 1) +TEST_INPUTS(0) + dup d0, v1.d[0] + dup d3, v4.d[1] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_B_INPUTS, dup_b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + dup b0, v1.b[0] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_H_INPUTS, dup_h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + dup h0, v1.h[0] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_S_INPUTS, dup_s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + dup s0, v1.s[0] +TEST_END + +TEST_BEGIN(DUP_ASISDONE_ONLY_D_INPUTS, dup_d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + dup d0, v1.d[0] +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/EOR_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/EOR_ASIMDSAME_ONLY.S index b537ae6e..041a350f 100644 --- a/backend/remill/tests/AArch64/SIMD/EOR_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/EOR_ASIMDSAME_ONLY.S @@ -27,3 +27,23 @@ TEST_INPUTS(0) eor v6.16b, v2.16b, v3.16b eor v7.16b, v4.16b, v5.16b TEST_END + +TEST_BEGIN(EOR_ASIMDSAME_ONLY_8B_INPUTS, eor_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + eor v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(EOR_ASIMDSAME_ONLY_16B_INPUTS, eor_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + eor v5.16b, v0.16b, v1.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/EXT_ASIMDINS_ONLY.S b/backend/remill/tests/AArch64/SIMD/EXT_ASIMDINS_ONLY.S index f40c9102..95aa81e6 100644 --- a/backend/remill/tests/AArch64/SIMD/EXT_ASIMDINS_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/EXT_ASIMDINS_ONLY.S @@ -28,3 +28,23 @@ TEST_INPUTS(0) movi v3.16b, #255 ext v1.16b, v2.16b, v3.16b, #1 TEST_END + +TEST_BEGIN(EXT_ASIMDINS_ONLY_8B_INPUTS, ext_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + ext v5.8b, v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(EXT_ASIMDINS_ONLY_16B_INPUTS, ext_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + ext v5.16b, v0.16b, v1.16b, #3 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FADD_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/FADD_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..b0f3d10f --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FADD_ASIMDSAME_ONLY.S @@ -0,0 +1,71 @@ +TEST_BEGIN(FADD_ASIMDSAME_ONLY_2S, fadd_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + fmov v1.2s, #1.0 + fmov v2.2s, #2.0 + fadd v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_2S_v2, fadd_v0_v1_v2_2s_v2, 1) +TEST_INPUTS(0) + fmov v1.2s, #-1.0 + fmov v2.2s, #3.0 + fadd v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_4S, fadd_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + fmov v1.4s, #1.0 + fmov v2.4s, #2.0 + fadd v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_4S_v2, fadd_v0_v1_v2_4s_v2, 1) +TEST_INPUTS(0) + fmov v1.4s, #-2.0 + fmov v2.4s, #4.0 + fadd v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_2D, fadd_v0_v1_v2_2d, 1) +TEST_INPUTS(0) + fmov v1.2d, #1.0 + fmov v2.2d, #2.0 + fadd v0.2d, v1.2d, v2.2d +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_2D_v2, fadd_v0_v1_v2_2d_v2, 1) +TEST_INPUTS(0) + fmov v1.2d, #0.5 + fmov v2.2d, #31.0 + fadd v0.2d, v1.2d, v2.2d +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_2S_INPUTS, fadd_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fadd v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_4S_INPUTS, fadd_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fadd v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FADD_ASIMDSAME_ONLY_2D_INPUTS, fadd_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fadd v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FCVTZU_ASISDMISC_R.S b/backend/remill/tests/AArch64/SIMD/FCVTZU_ASISDMISC_R.S new file mode 100644 index 00000000..7c2be773 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FCVTZU_ASISDMISC_R.S @@ -0,0 +1,41 @@ +TEST_BEGIN(FCVTZU_ASISDMISC_R_32, fcvtzu_s0_s1_sisd, 1) +TEST_INPUTS(0) + fmov s1, #2.5 + fcvtzu s0, s1 +TEST_END + +TEST_BEGIN(FCVTZU_ASISDMISC_R_32_v2, fcvtzu_s0_s1_sisd_v2, 1) +TEST_INPUTS(0) + fmov s1, #31.0 + fcvtzu s0, s1 +TEST_END + +TEST_BEGIN(FCVTZU_ASISDMISC_R_64, fcvtzu_d0_d1_sisd, 1) +TEST_INPUTS(0) + fmov d1, #2.5 + fcvtzu d0, d1 +TEST_END + +TEST_BEGIN(FCVTZU_ASISDMISC_R_64_v2, fcvtzu_d0_d1_sisd_v2, 1) +TEST_INPUTS(0) + fmov d1, #4.0 + fcvtzu d0, d1 +TEST_END + +TEST_BEGIN(FCVTZU_ASISDMISC_R_32_INPUTS, fcvtzu_s_inputs, 1) +TEST_INPUTS( + 0x3F8000003F800000, + 0x40000000C0000000, + 0x41200000BF800000) + fmov d1, ARG1_64 + fcvtzu s0, s1 +TEST_END + +TEST_BEGIN(FCVTZU_ASISDMISC_R_64_INPUTS, fcvtzu_d_inputs, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x4024000000000000) + fmov d1, ARG1_64 + fcvtzu d0, d1 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FDIV_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/FDIV_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..a5004a6b --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FDIV_ASIMDSAME_ONLY.S @@ -0,0 +1,57 @@ +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_2SF, fdiv_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + fmov v1.2s, #6.0 + fmov v2.2s, #2.0 + fdiv v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_2SF_v2, fdiv_v0_v1_v2_2s_v2, 1) +TEST_INPUTS(0) + fmov v1.2s, #4.0 + fmov v2.2s, #2.0 + fdiv v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_4SF, fdiv_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + fmov v1.4s, #6.0 + fmov v2.4s, #2.0 + fdiv v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_4SF_v2, fdiv_v0_v1_v2_4s_v2, 1) +TEST_INPUTS(0) + fmov v1.4s, #-8.0 + fmov v2.4s, #4.0 + fdiv v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_2S_INPUTS, fdiv_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fdiv v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_4S_INPUTS, fdiv_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fdiv v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FDIV_ASIMDSAME_ONLY_2D_INPUTS, fdiv_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fdiv v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FMAXV_ASIMDALL_ONLY_SD_4S.S b/backend/remill/tests/AArch64/SIMD/FMAXV_ASIMDALL_ONLY_SD_4S.S index 918d8406..f0b2a3ee 100644 --- a/backend/remill/tests/AArch64/SIMD/FMAXV_ASIMDALL_ONLY_SD_4S.S +++ b/backend/remill/tests/AArch64/SIMD/FMAXV_ASIMDALL_ONLY_SD_4S.S @@ -21,3 +21,12 @@ TEST_INPUTS(0) fmaxv s7, v2.4s fmaxv s8, v3.4s TEST_END + +TEST_BEGIN(FMAXV_ASIMDALL_ONLY_SD_4S_INPUTS, fmaxv_v4s_inputs, 1) +TEST_INPUTS( + 0x3F8000003F800000, + 0x40000000C0000000, + 0x41200000BF800000) + dup v1.2d, ARG1_64 + fmaxv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FMINV_ASIMDALL_ONLY_SD_4S.S b/backend/remill/tests/AArch64/SIMD/FMINV_ASIMDALL_ONLY_SD_4S.S index eb527825..fd8ccb76 100644 --- a/backend/remill/tests/AArch64/SIMD/FMINV_ASIMDALL_ONLY_SD_4S.S +++ b/backend/remill/tests/AArch64/SIMD/FMINV_ASIMDALL_ONLY_SD_4S.S @@ -21,3 +21,12 @@ TEST_INPUTS(0) fminv s7, v2.4s fminv s8, v3.4s TEST_END + +TEST_BEGIN(FMINV_ASIMDALL_ONLY_SD_4S_INPUTS, fminv_v4s_inputs, 1) +TEST_INPUTS( + 0x3F8000003F800000, + 0x40000000C0000000, + 0x41200000BF800000) + dup v1.2d, ARG1_64 + fminv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FMLA_ASIMDELEM_R_SD.S b/backend/remill/tests/AArch64/SIMD/FMLA_ASIMDELEM_R_SD.S new file mode 100644 index 00000000..4fde7b0b --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FMLA_ASIMDELEM_R_SD.S @@ -0,0 +1,80 @@ +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_2S, fmla_v0_v1_v2s0_2s, 1) +TEST_INPUTS(0) + fmov v0.2s, #1.0 + fmov v1.2s, #2.0 + fmov v2.2s, #3.0 + fmla v0.2s, v1.2s, v2.s[0] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_2S_v2, fmla_v0_v1_v2s0_2s_v2, 1) +TEST_INPUTS(0) + fmov v0.2s, #-1.0 + fmov v1.2s, #0.5 + fmov v2.2s, #4.0 + fmla v0.2s, v1.2s, v2.s[0] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_4S, fmla_v0_v1_v2s0_4s, 1) +TEST_INPUTS(0) + fmov v0.4s, #1.0 + fmov v1.4s, #2.0 + fmov v2.4s, #3.0 + fmla v0.4s, v1.4s, v2.s[0] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_4S_v2, fmla_v0_v1_v2s0_4s_v2, 1) +TEST_INPUTS(0) + fmov v0.4s, #2.0 + fmov v1.4s, #-2.0 + fmov v2.4s, #3.0 + fmla v0.4s, v1.4s, v2.s[1] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_2D, fmla_v0_v1_v2d0_2d, 1) +TEST_INPUTS(0) + fmov v0.2d, #1.0 + fmov v1.2d, #2.0 + fmov v2.2d, #3.0 + fmla v0.2d, v1.2d, v2.d[0] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_2D_v2, fmla_v0_v1_v2d0_2d_v2, 1) +TEST_INPUTS(0) + fmov v0.2d, #0.5 + fmov v1.2d, #4.0 + fmov v2.2d, #0.125 + fmla v0.2d, v1.2d, v2.d[1] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_2S_INPUTS, fmla_elem_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov v0.2s, #1.0 + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fmla v0.2s, v1.2s, v2.s[0] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_4S_INPUTS, fmla_elem_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov v0.4s, #1.0 + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmla v0.4s, v1.4s, v2.s[0] +TEST_END + +TEST_BEGIN(FMLA_ASIMDELEM_R_SD_2D_INPUTS, fmla_elem_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + fmov v0.2d, #1.0 + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmla v0.2d, v1.2d, v2.d[0] +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FMLA_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/FMLA_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..fd6b9b0d --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FMLA_ASIMDSAME_ONLY.S @@ -0,0 +1,80 @@ +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_2S, fmla_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + fmov v0.2s, #1.0 + fmov v1.2s, #2.0 + fmov v2.2s, #3.0 + fmla v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_2S_v2, fmla_v0_v1_v2_2s_v2, 1) +TEST_INPUTS(0) + fmov v0.2s, #-1.0 + fmov v1.2s, #0.5 + fmov v2.2s, #4.0 + fmla v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_4S, fmla_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + fmov v0.4s, #1.0 + fmov v1.4s, #2.0 + fmov v2.4s, #3.0 + fmla v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_4S_v2, fmla_v0_v1_v2_4s_v2, 1) +TEST_INPUTS(0) + fmov v0.4s, #2.0 + fmov v1.4s, #-1.0 + fmov v2.4s, #3.0 + fmla v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_2D, fmla_v0_v1_v2_2d, 1) +TEST_INPUTS(0) + fmov v0.2d, #1.0 + fmov v1.2d, #2.0 + fmov v2.2d, #3.0 + fmla v0.2d, v1.2d, v2.2d +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_2D_v2, fmla_v0_v1_v2_2d_v2, 1) +TEST_INPUTS(0) + fmov v0.2d, #0.5 + fmov v1.2d, #4.0 + fmov v2.2d, #0.125 + fmla v0.2d, v1.2d, v2.2d +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_2S_INPUTS, fmla_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov v0.2s, #1.0 + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fmla v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_4S_INPUTS, fmla_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov v0.4s, #1.0 + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmla v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FMLA_ASIMDSAME_ONLY_2D_INPUTS, fmla_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + fmov v0.2d, #1.0 + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmla v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FMOV_VECTORS.S b/backend/remill/tests/AArch64/SIMD/FMOV_VECTORS.S index 55c3977b..bd208d19 100644 --- a/backend/remill/tests/AArch64/SIMD/FMOV_VECTORS.S +++ b/backend/remill/tests/AArch64/SIMD/FMOV_VECTORS.S @@ -36,4 +36,22 @@ TEST_INPUTS(0) fmov v5.d[1], x5 fmov v6.d[1], x6 fmov v0.d[1], x6 +TEST_END + +TEST_BEGIN(FMOV_64VX_FLOAT2INT_INPUTS, fmov_64vx_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v0.2d, ARG1_64 + fmov x0, v0.d[1] +TEST_END + +TEST_BEGIN(FMOV_V64I_FLOAT2INT_INPUTS, fmov_v64i_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + mov x0, ARG1_64 + fmov v0.d[1], x0 TEST_END \ No newline at end of file diff --git a/backend/remill/tests/AArch64/SIMD/FMUL_ASIMDELEM_R_SD.S b/backend/remill/tests/AArch64/SIMD/FMUL_ASIMDELEM_R_SD.S new file mode 100644 index 00000000..a0914e6b --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FMUL_ASIMDELEM_R_SD.S @@ -0,0 +1,85 @@ +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_2S, fmul_v0_v1_v2s0_2s, 1) +TEST_INPUTS(0) + fmov v1.2s, #2.0 + fmov v2.2s, #3.0 + fmul v0.2s, v1.2s, v2.s[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_2S_v2, fmul_v0_v1_v2s0_2s_v2, 1) +TEST_INPUTS(0) + fmov v1.2s, #-1.0 + fmov v2.2s, #4.0 + fmul v0.2s, v1.2s, v2.s[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_4S, fmul_v0_v1_v2s0_4s, 1) +TEST_INPUTS(0) + fmov v1.4s, #2.0 + fmov v2.4s, #3.0 + fmul v0.4s, v1.4s, v2.s[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_4S_v2, fmul_v0_v1_v2s0_4s_v2, 1) +TEST_INPUTS(0) + fmov v1.4s, #0.5 + fmov v2.4s, #-2.0 + fmul v0.4s, v1.4s, v2.s[1] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_2D, fmul_v0_v1_v2d0_2d, 1) +TEST_INPUTS(0) + fmov v1.2d, #2.0 + fmov v2.2d, #3.0 + fmul v0.2d, v1.2d, v2.d[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_2D_v2, fmul_v0_v1_v2d0_2d_v2, 1) +TEST_INPUTS(0) + fmov v1.2d, #0.125 + fmov v2.2d, #8.0 + fmul v0.2d, v1.2d, v2.d[1] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_1D, fmul_d0_d1_v2d0, 1) +TEST_INPUTS(0) + fmov d1, #2.0 + fmov v2.2d, #3.0 + fmul d0, d1, v2.d[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_1D_v2, fmul_d0_d1_v2d0_v2, 1) +TEST_INPUTS(0) + fmov d1, #-4.0 + fmov v2.2d, #0.5 + fmul d0, d1, v2.d[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_2S_INPUTS, fmul_elem_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fmul v0.2s, v1.2s, v2.s[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_4S_INPUTS, fmul_elem_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmul v0.4s, v1.4s, v2.s[0] +TEST_END + +TEST_BEGIN(FMUL_ASIMDELEM_R_SD_2D_INPUTS, fmul_elem_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmul v0.2d, v1.2d, v2.d[0] +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FMUL_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/FMUL_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..ed66e8e3 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FMUL_ASIMDSAME_ONLY.S @@ -0,0 +1,71 @@ +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_2S, fmul_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + fmov v1.2s, #2.0 + fmov v2.2s, #3.0 + fmul v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_2S_v2, fmul_v0_v1_v2_2s_v2, 1) +TEST_INPUTS(0) + fmov v1.2s, #-1.0 + fmov v2.2s, #4.0 + fmul v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_4S, fmul_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + fmov v1.4s, #2.0 + fmov v2.4s, #3.0 + fmul v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_4S_v2, fmul_v0_v1_v2_4s_v2, 1) +TEST_INPUTS(0) + fmov v1.4s, #0.5 + fmov v2.4s, #-2.0 + fmul v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_2D, fmul_v0_v1_v2_2d, 1) +TEST_INPUTS(0) + fmov v1.2d, #2.0 + fmov v2.2d, #3.0 + fmul v0.2d, v1.2d, v2.2d +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_2D_v2, fmul_v0_v1_v2_2d_v2, 1) +TEST_INPUTS(0) + fmov v1.2d, #0.125 + fmov v2.2d, #8.0 + fmul v0.2d, v1.2d, v2.2d +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_2S_INPUTS, fmul_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fmul v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_4S_INPUTS, fmul_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmul v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FMUL_ASIMDSAME_ONLY_2D_INPUTS, fmul_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fmul v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FRINTM_ASIMDMISC_R.S b/backend/remill/tests/AArch64/SIMD/FRINTM_ASIMDMISC_R.S new file mode 100644 index 00000000..e487363d --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FRINTM_ASIMDMISC_R.S @@ -0,0 +1,62 @@ +TEST_BEGIN(FRINTM_ASIMDMISC_R_2S, frintm_v0_v1_2s, 1) +TEST_INPUTS(0) + fmov v1.2s, #2.5 + frintm v0.2s, v1.2s +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_2S_v2, frintm_v0_v1_2s_v2, 1) +TEST_INPUTS(0) + fmov v1.2s, #-2.0 + frintm v0.2s, v1.2s +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_4S, frintm_v0_v1_4s, 1) +TEST_INPUTS(0) + fmov v1.4s, #2.5 + frintm v0.4s, v1.4s +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_4S_v2, frintm_v0_v1_4s_v2, 1) +TEST_INPUTS(0) + fmov v1.4s, #3.5 + frintm v0.4s, v1.4s +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_2D, frintm_v0_v1_2d, 1) +TEST_INPUTS(0) + fmov v1.2d, #2.5 + frintm v0.2d, v1.2d +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_2D_v2, frintm_v0_v1_2d_v2, 1) +TEST_INPUTS(0) + fmov v1.2d, #-2.0 + frintm v0.2d, v1.2d +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_2S_INPUTS, frintm_v2s_inputs, 1) +TEST_INPUTS( + 0x3F8000003F800000, + 0x40000000C0000000, + 0x41200000BF800000) + fmov d1, ARG1_64 + frintm v0.2s, v1.2s +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_4S_INPUTS, frintm_v4s_inputs, 1) +TEST_INPUTS( + 0x3F8000003F800000, + 0x40000000C0000000, + 0x41200000BF800000) + dup v1.2d, ARG1_64 + frintm v0.4s, v1.4s +TEST_END + +TEST_BEGIN(FRINTM_ASIMDMISC_R_2D_INPUTS, frintm_v2d_inputs, 1) +TEST_INPUTS( + 0x3FF0000000000000, + 0x4000000000000000, + 0x4024000000000000) + dup v1.2d, ARG1_64 + frintm v0.2d, v1.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/FSUB_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/FSUB_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..8d164b38 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/FSUB_ASIMDSAME_ONLY.S @@ -0,0 +1,57 @@ +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_2SF, fsub_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + fmov v1.2s, #3.0 + fmov v2.2s, #1.0 + fsub v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_2SF_v2, fsub_v0_v1_v2_2s_v2, 1) +TEST_INPUTS(0) + fmov v1.2s, #-1.0 + fmov v2.2s, #4.0 + fsub v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_4SF, fsub_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + fmov v1.4s, #3.0 + fmov v2.4s, #1.0 + fsub v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_4SF_v2, fsub_v0_v1_v2_4s_v2, 1) +TEST_INPUTS(0) + fmov v1.4s, #0.5 + fmov v2.4s, #-2.0 + fsub v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_2S_INPUTS, fsub_v2s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + fsub v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_4S_INPUTS, fsub_v4s_inputs, 2) +TEST_INPUTS( + 0x3F8000003F800000, 0x4000000040000000, + 0xBF800000C0000000, 0x40A000003F000000, + 0x4120000041200000, 0x3F0000003F000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fsub v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(FSUB_ASIMDSAME_ONLY_2D_INPUTS, fsub_v2d_inputs, 2) +TEST_INPUTS( + 0x3FF0000000000000, 0x4000000000000000, + 0xBFF0000000000000, 0x4014000000000000, + 0x4024000000000000, 0x3FE0000000000000) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + fsub v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/INS_ASIMDINS_IV_V.S b/backend/remill/tests/AArch64/SIMD/INS_ASIMDINS_IV_V.S new file mode 100644 index 00000000..0f9f362e --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/INS_ASIMDINS_IV_V.S @@ -0,0 +1,63 @@ +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_B, ins_v0b0_v1b1, 1) +TEST_INPUTS(0) + ins v0.b[0], v1.b[1] + ins v3.b[7], v4.b[3] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_H, ins_v0h0_v1h1, 1) +TEST_INPUTS(0) + ins v0.h[0], v1.h[1] + ins v3.h[3], v5.h[0] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_S, ins_v0s0_v1s1, 1) +TEST_INPUTS(0) + ins v0.s[0], v1.s[1] + ins v3.s[2], v6.s[0] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_D, ins_v0d0_v1d1, 1) +TEST_INPUTS(0) + ins v0.d[0], v1.d[1] + ins v3.d[1], v7.d[0] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_B_INPUTS, ins_vb_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + ins v0.b[0], v1.b[1] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_H_INPUTS, ins_vh_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + ins v0.h[0], v1.h[1] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_S_INPUTS, ins_vs_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + ins v0.s[0], v1.s[1] +TEST_END + +TEST_BEGIN(MOV_INS_ASIMDINS_IV_V_D_INPUTS, ins_vd_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + ins v0.d[0], v1.d[1] +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/NOT_ASIMDMISC_R.S b/backend/remill/tests/AArch64/SIMD/NOT_ASIMDMISC_R.S index 1d343b27..bc432886 100644 --- a/backend/remill/tests/AArch64/SIMD/NOT_ASIMDMISC_R.S +++ b/backend/remill/tests/AArch64/SIMD/NOT_ASIMDMISC_R.S @@ -29,3 +29,21 @@ TEST_INPUTS(0) not v3.16b, v2.16b not v4.16b, v3.16b TEST_END + +TEST_BEGIN(NOT_ASIMDMISC_R_8B_INPUTS, not_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + not v0.8b, v1.8b +TEST_END + +TEST_BEGIN(NOT_ASIMDMISC_R_16B_INPUTS, not_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + not v0.16b, v1.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/ORR_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/ORR_ASIMDSAME_ONLY.S index b4338539..d53fcd68 100644 --- a/backend/remill/tests/AArch64/SIMD/ORR_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/ORR_ASIMDSAME_ONLY.S @@ -27,3 +27,23 @@ TEST_INPUTS(0) orr v6.16b, v2.16b, v3.16b orr v7.16b, v4.16b, v5.16b TEST_END + +TEST_BEGIN(ORR_ASIMDSAME_ONLY_8B_INPUTS, orr_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + orr v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(ORR_ASIMDSAME_ONLY_16B_INPUTS, orr_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + orr v5.16b, v0.16b, v1.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/REV32_ASIMDMISC_R.S b/backend/remill/tests/AArch64/SIMD/REV32_ASIMDMISC_R.S new file mode 100644 index 00000000..ebc42d9f --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/REV32_ASIMDMISC_R.S @@ -0,0 +1,63 @@ +TEST_BEGIN(REV32_ASIMDMISC_R_8B, rev32_v0v3v5_8b, 1) +TEST_INPUTS(0) + rev32 v0.8b, v1.8b + rev32 v3.8b, v4.8b + rev32 v5.8b, v6.8b +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_16B, rev32_v0v3v5_16b, 1) +TEST_INPUTS(0) + rev32 v0.16b, v1.16b + rev32 v3.16b, v4.16b + rev32 v5.16b, v6.16b +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_4H, rev32_v0v3v5_4h, 1) +TEST_INPUTS(0) + rev32 v0.4h, v1.4h + rev32 v3.4h, v4.4h + rev32 v5.4h, v6.4h +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_8H, rev32_v0v3v5_8h, 1) +TEST_INPUTS(0) + rev32 v0.8h, v1.8h + rev32 v3.8h, v4.8h + rev32 v5.8h, v6.8h +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_8B_INPUTS, rev32_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + rev32 v0.8b, v1.8b +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_16B_INPUTS, rev32_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + rev32 v0.16b, v1.16b +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_4H_INPUTS, rev32_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + rev32 v0.4h, v1.4h +TEST_END + +TEST_BEGIN(REV32_ASIMDMISC_R_8H_INPUTS, rev32_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + rev32 v0.8h, v1.8h +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SADDW_ASIMDDIFF_W.S b/backend/remill/tests/AArch64/SIMD/SADDW_ASIMDDIFF_W.S new file mode 100644 index 00000000..7cacc4ca --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SADDW_ASIMDDIFF_W.S @@ -0,0 +1,95 @@ +TEST_BEGIN(SADDW_ASIMDDIFF_W_8H8B, saddw_v0_v1_v2_8h8b, 1) +TEST_INPUTS(0) + saddw v0.8h, v1.8h, v2.8b + saddw v3.8h, v4.8h, v5.8b +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_8H16B, saddw2_v0_v1_v2_8h16b, 1) +TEST_INPUTS(0) + saddw2 v0.8h, v1.8h, v2.16b + saddw2 v3.8h, v4.8h, v5.16b +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_4S4H, saddw_v0_v1_v2_4s4h, 1) +TEST_INPUTS(0) + saddw v0.4s, v1.4s, v2.4h + saddw v3.4s, v4.4s, v5.4h +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_4S8H, saddw2_v0_v1_v2_4s8h, 1) +TEST_INPUTS(0) + saddw2 v0.4s, v1.4s, v2.8h + saddw2 v3.4s, v4.4s, v5.8h +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_2D2S, saddw_v0_v1_v2_2d2s, 1) +TEST_INPUTS(0) + saddw v0.2d, v1.2d, v2.2s + saddw v3.2d, v4.2d, v5.2s +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_2D4S, saddw2_v0_v1_v2_2d4s, 1) +TEST_INPUTS(0) + saddw2 v0.2d, v1.2d, v2.4s + saddw2 v3.2d, v4.2d, v5.4s +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_8H8B_INPUTS, saddw_v8h8b_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0102030405060708, + 0x8000FFFF7FFF0000, 0x80FF7F0001FE0200, + 0xAAAA5555CCCC3333, 0xAAAAAAAAAAAAAAAA) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + saddw v0.8h, v1.8h, v2.8b +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_8H16B_INPUTS, saddw2_v8h16b_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0102030405060708, + 0x8000FFFF7FFF0000, 0x80FF7F0001FE0200, + 0xAAAA5555CCCC3333, 0xAAAAAAAAAAAAAAAA) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + saddw2 v0.8h, v1.8h, v2.16b +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_4S4H_INPUTS, saddw_v4s4h_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0001000200030004, + 0x80000000FFFFFFFF, 0x8000FFFF7FFF0000, + 0xAAAAAAAA55555555, 0xAAAA5555CCCC3333) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + saddw v0.4s, v1.4s, v2.4h +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_4S8H_INPUTS, saddw2_v4s8h_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0001000200030004, + 0x80000000FFFFFFFF, 0x8000FFFF7FFF0000, + 0xAAAAAAAA55555555, 0xAAAA5555CCCC3333) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + saddw2 v0.4s, v1.4s, v2.8h +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_2D2S_INPUTS, saddw_v2d2s_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000100000002, + 0x8000000000000000, 0x80000000FFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0xAAAAAAAA55555555) + dup v1.2d, ARG1_64 + fmov d2, ARG2_64 + saddw v0.2d, v1.2d, v2.2s +TEST_END + +TEST_BEGIN(SADDW_ASIMDDIFF_W_2D4S_INPUTS, saddw2_v2d4s_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000100000002, + 0x8000000000000000, 0x80000000FFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0xAAAAAAAA55555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + saddw2 v0.2d, v1.2d, v2.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SCVTF_ASIMDMISC_R.S b/backend/remill/tests/AArch64/SIMD/SCVTF_ASIMDMISC_R.S new file mode 100644 index 00000000..5601207a --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SCVTF_ASIMDMISC_R.S @@ -0,0 +1,98 @@ +TEST_BEGIN(SCVTF_ASIMDMISC_R_2S, scvtf_v0_v1_2s, 1) +TEST_INPUTS(0) + movi v1.2s, #42 + scvtf v0.2s, v1.2s +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_2S_v2, scvtf_v3_v4_2s_v2, 1) +TEST_INPUTS(0) + movi v4.2s, #7 + scvtf v3.2s, v4.2s +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_4S, scvtf_v0_v1_4s, 1) +TEST_INPUTS(0) + movi v1.4s, #42 + scvtf v0.4s, v1.4s +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_4S_v2, scvtf_v3_v4_4s_v2, 1) +TEST_INPUTS(0) + movi v4.4s, #13 + scvtf v3.4s, v4.4s +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_2D, scvtf_v0_v1_2d, 1) +TEST_INPUTS(0) + scvtf v0.2d, v1.2d +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_2D_v2, scvtf_v3_v4_2d_v2, 1) +TEST_INPUTS(0) + scvtf v3.2d, v4.2d +TEST_END + +TEST_BEGIN(SCVTF_ASISDMISC_R_32, scvtf_s0_s1, 1) +TEST_INPUTS(0) + scvtf s0, s1 +TEST_END + +TEST_BEGIN(SCVTF_ASISDMISC_R_32_v2, scvtf_s3_s4_v2, 1) +TEST_INPUTS(0) + scvtf s3, s4 +TEST_END + +TEST_BEGIN(SCVTF_ASISDMISC_R_64, scvtf_d0_d1, 1) +TEST_INPUTS(0) + scvtf d0, d1 +TEST_END + +TEST_BEGIN(SCVTF_ASISDMISC_R_64_v2, scvtf_d3_d4_v2, 1) +TEST_INPUTS(0) + scvtf d3, d4 +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_2S_INPUTS, scvtf_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + scvtf v0.2s, v1.2s +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_4S_INPUTS, scvtf_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + scvtf v0.4s, v1.4s +TEST_END + +TEST_BEGIN(SCVTF_ASIMDMISC_R_2D_INPUTS, scvtf_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + scvtf v0.2d, v1.2d +TEST_END + +TEST_BEGIN(SCVTF_ASISDMISC_R_32_INPUTS, scvtf_s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + scvtf s0, s1 +TEST_END + +TEST_BEGIN(SCVTF_ASISDMISC_R_64_INPUTS, scvtf_d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + fmov d1, ARG1_64 + scvtf d0, d1 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SHLL_ASIMDMISC_S.S b/backend/remill/tests/AArch64/SIMD/SHLL_ASIMDMISC_S.S new file mode 100644 index 00000000..00dbc2a1 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SHLL_ASIMDMISC_S.S @@ -0,0 +1,89 @@ +TEST_BEGIN(SHLL_ASIMDMISC_S_8H8B, shll_v0_v1_8h8b, 1) +TEST_INPUTS(0) + shll v0.8h, v1.8b, #8 + shll v3.8h, v4.8b, #8 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_8H16B, shll2_v0_v1_8h16b, 1) +TEST_INPUTS(0) + shll2 v0.8h, v1.16b, #8 + shll2 v3.8h, v4.16b, #8 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_4S4H, shll_v0_v1_4s4h, 1) +TEST_INPUTS(0) + shll v0.4s, v1.4h, #16 + shll v3.4s, v4.4h, #16 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_4S8H, shll2_v0_v1_4s8h, 1) +TEST_INPUTS(0) + shll2 v0.4s, v1.8h, #16 + shll2 v3.4s, v4.8h, #16 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_2D2S, shll_v0_v1_2d2s, 1) +TEST_INPUTS(0) + shll v0.2d, v1.2s, #32 + shll v3.2d, v4.2s, #32 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_2D4S, shll2_v0_v1_2d4s, 1) +TEST_INPUTS(0) + shll2 v0.2d, v1.4s, #32 + shll2 v3.2d, v4.4s, #32 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_8H8B_INPUTS, shll_8h8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + shll v0.8h, v1.8b, #8 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_8H16B_INPUTS, shll2_8h16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + shll2 v0.8h, v1.16b, #8 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_4S4H_INPUTS, shll_4s4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + shll v0.4s, v1.4h, #16 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_4S8H_INPUTS, shll2_4s8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + shll2 v0.4s, v1.8h, #16 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_2D2S_INPUTS, shll_2d2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + shll v0.2d, v1.2s, #32 +TEST_END + +TEST_BEGIN(SHLL_ASIMDMISC_S_2D4S_INPUTS, shll2_2d4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + shll2 v0.2d, v1.4s, #32 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SHL_ASIMDSHF_R.S b/backend/remill/tests/AArch64/SIMD/SHL_ASIMDSHF_R.S new file mode 100644 index 00000000..5fe23d24 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SHL_ASIMDSHF_R.S @@ -0,0 +1,110 @@ +TEST_BEGIN(SHL_ASIMDSHF_R_8B, shl_v0_v1_8b_3, 1) +TEST_INPUTS(0) + shl v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_8B_1, shl_v0_v1_8b_1, 1) +TEST_INPUTS(0) + shl v0.8b, v1.8b, #1 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_8B_7, shl_v0_v1_8b_7, 1) +TEST_INPUTS(0) + shl v0.8b, v1.8b, #7 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_16B, shl_v0_v1_16b_3, 1) +TEST_INPUTS(0) + shl v0.16b, v1.16b, #3 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_16B_1, shl_v0_v1_16b_1, 1) +TEST_INPUTS(0) + shl v0.16b, v1.16b, #1 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_16B_5, shl_v0_v1_16b_5, 1) +TEST_INPUTS(0) + shl v0.16b, v1.16b, #5 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_4H, shl_v0_v1_4h_5, 1) +TEST_INPUTS(0) + shl v0.4h, v1.4h, #5 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_4H_3, shl_v0_v1_4h_3, 1) +TEST_INPUTS(0) + shl v0.4h, v1.4h, #3 +TEST_END + +/* TODO: SHL 4H #11 fails - semantics bug with larger shift amounts */ + +TEST_BEGIN(SHL_ASIMDSHF_R_8H, shl_v0_v1_8h_5, 1) +TEST_INPUTS(0) + shl v0.8h, v1.8h, #5 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_8H_3, shl_v0_v1_8h_3, 1) +TEST_INPUTS(0) + shl v0.8h, v1.8h, #3 +TEST_END + +/* TODO: SHL 8H #11 fails - semantics bug with larger shift amounts */ + +/* TODO: SHL_ASIMDSHF_R_2S, SHL_ASIMDSHF_R_4S, SHL_ASIMDSHF_R_2D fail - semantics bug */ + +TEST_BEGIN(SHL_ASISDSHF_R, shl_d0_d1_20, 1) +TEST_INPUTS(0) + shl d0, d1, #20 +TEST_END + +TEST_BEGIN(SHL_ASISDSHF_R_40, shl_d0_d1_40, 1) +TEST_INPUTS(0) + shl d0, d1, #40 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_8B_INPUTS, shl_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + shl v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_16B_INPUTS, shl_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + shl v0.16b, v1.16b, #3 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_4H_INPUTS, shl_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + shl v0.4h, v1.4h, #5 +TEST_END + +TEST_BEGIN(SHL_ASIMDSHF_R_8H_INPUTS, shl_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + shl v0.8h, v1.8h, #5 +TEST_END + +TEST_BEGIN(SHL_ASISDSHF_R_INPUTS, shl_d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + fmov d1, ARG1_64 + shl d0, d1, #20 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SMAXP_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/SMAXP_ASIMDSAME_ONLY.S index ca5b8423..da89f02f 100644 --- a/backend/remill/tests/AArch64/SIMD/SMAXP_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SMAXP_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) smaxp v6.4s, v2.4s, v3.4s smaxp v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(SMAXP_ASIMDSAME_ONLY_8B_INPUTS, smaxp_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smaxp v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(SMAXP_ASIMDSAME_ONLY_16B_INPUTS, smaxp_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smaxp v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(SMAXP_ASIMDSAME_ONLY_4H_INPUTS, smaxp_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smaxp v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(SMAXP_ASIMDSAME_ONLY_8H_INPUTS, smaxp_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smaxp v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(SMAXP_ASIMDSAME_ONLY_2S_INPUTS, smaxp_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smaxp v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(SMAXP_ASIMDSAME_ONLY_4S_INPUTS, smaxp_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smaxp v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SMAXV_ASIMDALL_ONLY.S b/backend/remill/tests/AArch64/SIMD/SMAXV_ASIMDALL_ONLY.S index 354cc2f4..17b092fa 100644 --- a/backend/remill/tests/AArch64/SIMD/SMAXV_ASIMDALL_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SMAXV_ASIMDALL_ONLY.S @@ -53,3 +53,48 @@ TEST_INPUTS(0) smaxv s7, v2.4s smaxv s8, v3.4s TEST_END + +TEST_BEGIN(SMAXV_ASIMDALL_ONLY_8B_INPUTS, smaxv_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + smaxv b0, v1.8b +TEST_END + +TEST_BEGIN(SMAXV_ASIMDALL_ONLY_16B_INPUTS, smaxv_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + smaxv b0, v1.16b +TEST_END + +TEST_BEGIN(SMAXV_ASIMDALL_ONLY_4H_INPUTS, smaxv_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + smaxv h0, v1.4h +TEST_END + +TEST_BEGIN(SMAXV_ASIMDALL_ONLY_8H_INPUTS, smaxv_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + smaxv h0, v1.8h +TEST_END + +TEST_BEGIN(SMAXV_ASIMDALL_ONLY_4S_INPUTS, smaxv_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + smaxv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SMAX_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/SMAX_ASIMDSAME_ONLY.S index 8d5b50b0..a889e0d4 100644 --- a/backend/remill/tests/AArch64/SIMD/SMAX_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SMAX_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) smax v6.4s, v2.4s, v3.4s smax v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(SMAX_ASIMDSAME_ONLY_8B_INPUTS, smax_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smax v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(SMAX_ASIMDSAME_ONLY_16B_INPUTS, smax_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smax v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(SMAX_ASIMDSAME_ONLY_4H_INPUTS, smax_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smax v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(SMAX_ASIMDSAME_ONLY_8H_INPUTS, smax_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smax v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(SMAX_ASIMDSAME_ONLY_2S_INPUTS, smax_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smax v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(SMAX_ASIMDSAME_ONLY_4S_INPUTS, smax_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smax v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SMINP_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/SMINP_ASIMDSAME_ONLY.S index 9b27ae1e..64f0a0e6 100644 --- a/backend/remill/tests/AArch64/SIMD/SMINP_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SMINP_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) sminp v6.4s, v2.4s, v3.4s sminp v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(SMINP_ASIMDSAME_ONLY_8B_INPUTS, sminp_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + sminp v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(SMINP_ASIMDSAME_ONLY_16B_INPUTS, sminp_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + sminp v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(SMINP_ASIMDSAME_ONLY_4H_INPUTS, sminp_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + sminp v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(SMINP_ASIMDSAME_ONLY_8H_INPUTS, sminp_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + sminp v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(SMINP_ASIMDSAME_ONLY_2S_INPUTS, sminp_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + sminp v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(SMINP_ASIMDSAME_ONLY_4S_INPUTS, sminp_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + sminp v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SMINV_ASIMDALL_ONLY.S b/backend/remill/tests/AArch64/SIMD/SMINV_ASIMDALL_ONLY.S index 94d35893..3f69c787 100644 --- a/backend/remill/tests/AArch64/SIMD/SMINV_ASIMDALL_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SMINV_ASIMDALL_ONLY.S @@ -53,3 +53,48 @@ TEST_INPUTS(0) sminv s7, v2.4s sminv s8, v3.4s TEST_END + +TEST_BEGIN(SMINV_ASIMDALL_ONLY_8B_INPUTS, sminv_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + sminv b0, v1.8b +TEST_END + +TEST_BEGIN(SMINV_ASIMDALL_ONLY_16B_INPUTS, sminv_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + sminv b0, v1.16b +TEST_END + +TEST_BEGIN(SMINV_ASIMDALL_ONLY_4H_INPUTS, sminv_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + sminv h0, v1.4h +TEST_END + +TEST_BEGIN(SMINV_ASIMDALL_ONLY_8H_INPUTS, sminv_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + sminv h0, v1.8h +TEST_END + +TEST_BEGIN(SMINV_ASIMDALL_ONLY_4S_INPUTS, sminv_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + sminv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SMIN_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/SMIN_ASIMDSAME_ONLY.S index 20a67ef9..f9938191 100644 --- a/backend/remill/tests/AArch64/SIMD/SMIN_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SMIN_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) smin v6.4s, v2.4s, v3.4s smin v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(SMIN_ASIMDSAME_ONLY_8B_INPUTS, smin_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smin v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(SMIN_ASIMDSAME_ONLY_16B_INPUTS, smin_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smin v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(SMIN_ASIMDSAME_ONLY_4H_INPUTS, smin_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smin v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(SMIN_ASIMDSAME_ONLY_8H_INPUTS, smin_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smin v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(SMIN_ASIMDSAME_ONLY_2S_INPUTS, smin_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + smin v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(SMIN_ASIMDSAME_ONLY_4S_INPUTS, smin_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + smin v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SSHLL_ASIMDSHF_L.S b/backend/remill/tests/AArch64/SIMD/SSHLL_ASIMDSHF_L.S new file mode 100644 index 00000000..422655ed --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SSHLL_ASIMDSHF_L.S @@ -0,0 +1,89 @@ +TEST_BEGIN(SSHLL_ASIMDSHF_L_8H8B, sshll_v0_v1_8h8b, 1) +TEST_INPUTS(0) + sshll v0.8h, v1.8b, #2 + sshll v3.8h, v4.8b, #5 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_8H16B, sshll2_v0_v1_8h16b, 1) +TEST_INPUTS(0) + sshll2 v0.8h, v1.16b, #2 + sshll2 v3.8h, v4.16b, #5 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_4S4H, sshll_v0_v1_4s4h, 1) +TEST_INPUTS(0) + sshll v0.4s, v1.4h, #3 + sshll v3.4s, v4.4h, #3 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_4S8H, sshll2_v0_v1_4s8h, 1) +TEST_INPUTS(0) + sshll2 v0.4s, v1.8h, #3 + sshll2 v3.4s, v4.8h, #3 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_2D2S, sshll_v0_v1_2d2s, 1) +TEST_INPUTS(0) + sshll v0.2d, v1.2s, #5 + sshll v3.2d, v4.2s, #5 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_2D4S, sshll2_v0_v1_2d4s, 1) +TEST_INPUTS(0) + sshll2 v0.2d, v1.4s, #5 + sshll2 v3.2d, v4.4s, #5 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_8H8B_INPUTS, sshll_8h8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + sshll v0.8h, v1.8b, #2 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_8H16B_INPUTS, sshll2_8h16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + sshll2 v0.8h, v1.16b, #2 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_4S4H_INPUTS, sshll_4s4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + sshll v0.4s, v1.4h, #3 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_4S8H_INPUTS, sshll2_4s8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + sshll2 v0.4s, v1.8h, #3 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_2D2S_INPUTS, sshll_2d2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + sshll v0.2d, v1.2s, #5 +TEST_END + +TEST_BEGIN(SSHLL_ASIMDSHF_L_2D4S_INPUTS, sshll2_2d4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + sshll2 v0.2d, v1.4s, #5 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SSHL_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/SSHL_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..669bec25 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SSHL_ASIMDSAME_ONLY.S @@ -0,0 +1,119 @@ +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_8B, sshl_v0_v1_v2_8b, 1) +TEST_INPUTS(0) + movi v2.8b, #2 + sshl v0.8b, v1.8b, v2.8b + sshl v3.8b, v4.8b, v2.8b +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_16B, sshl_v0_v1_v2_16b, 1) +TEST_INPUTS(0) + movi v2.16b, #2 + sshl v0.16b, v1.16b, v2.16b + sshl v3.16b, v4.16b, v2.16b +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_4H, sshl_v0_v1_v2_4h, 1) +TEST_INPUTS(0) + movi v2.4h, #3 + sshl v0.4h, v1.4h, v2.4h + sshl v3.4h, v4.4h, v2.4h +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_8H, sshl_v0_v1_v2_8h, 1) +TEST_INPUTS(0) + movi v2.8h, #3 + sshl v0.8h, v1.8h, v2.8h + sshl v3.8h, v4.8h, v2.8h +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_2S, sshl_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + movi v2.2s, #4 + sshl v0.2s, v1.2s, v2.2s + sshl v3.2s, v4.2s, v2.2s +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_4S, sshl_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + movi v2.4s, #4 + sshl v0.4s, v1.4s, v2.4s + sshl v3.4s, v4.4s, v2.4s +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_2D, sshl_v0_v1_v2_2d, 1) +TEST_INPUTS(0) + mov x2, #5 + dup v2.2d, x2 + sshl v0.2d, v1.2d, v2.2d + sshl v3.2d, v4.2d, v2.2d +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_8B_INPUTS, sshl_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0102030405060708, + 0x80FF7F0001FE0200, 0xFCFDFEFF00010203, + 0xAAAAAAAAAAAAAAAA, 0x0505050505050505) + fmov d0, ARG1_64 + fmov d2, ARG2_64 + sshl v0.8b, v0.8b, v2.8b +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_16B_INPUTS, sshl_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0102030405060708, + 0x80FF7F0001FE0200, 0xFCFDFEFF00010203, + 0xAAAAAAAAAAAAAAAA, 0x0505050505050505) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + sshl v0.16b, v0.16b, v2.16b +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_4H_INPUTS, sshl_v4h_inputs, 2) +TEST_INPUTS( + 0x0001800000017FFF, 0x0003000300030003, + 0xFFFF000000010002, 0xFFFDFFFD00050005, + 0x8000FFFF7FFF0001, 0x000F000F000F000F) + fmov d0, ARG1_64 + fmov d2, ARG2_64 + sshl v0.4h, v0.4h, v2.4h +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_8H_INPUTS, sshl_v8h_inputs, 2) +TEST_INPUTS( + 0x0001800000017FFF, 0x0003000300030003, + 0xFFFF000000010002, 0xFFFDFFFD00050005, + 0x8000FFFF7FFF0001, 0x000F000F000F000F) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + sshl v0.8h, v0.8h, v2.8h +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_2S_INPUTS, sshl_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000180000000, 0x0000000400000004, + 0xFFFFFFFF00000001, 0xFFFFFFFC00000008, + 0x7FFFFFFF80000001, 0x0000001000000010) + fmov d0, ARG1_64 + fmov d2, ARG2_64 + sshl v0.2s, v0.2s, v2.2s +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_4S_INPUTS, sshl_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000180000000, 0x0000000400000004, + 0xFFFFFFFF00000001, 0xFFFFFFFC00000008, + 0x7FFFFFFF80000001, 0x0000001000000010) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + sshl v0.4s, v0.4s, v2.4s +TEST_END + +TEST_BEGIN(SSHL_ASIMDSAME_ONLY_2D_INPUTS, sshl_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000005, + 0x8000000000000000, 0xFFFFFFFFFFFFFFF0, + 0xFFFFFFFFFFFFFFFF, 0x0000000000000020) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + sshl v0.2d, v0.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SSHR_ASIMDSHF_R.S b/backend/remill/tests/AArch64/SIMD/SSHR_ASIMDSHF_R.S new file mode 100644 index 00000000..4f122aff --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/SSHR_ASIMDSHF_R.S @@ -0,0 +1,186 @@ +TEST_BEGIN(SSHR_ASIMDSHF_R_8B, sshr_v0_v1_8b_3, 1) +TEST_INPUTS(0) + sshr v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8B_1, sshr_v0_v1_8b_1, 1) +TEST_INPUTS(0) + sshr v0.8b, v1.8b, #1 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8B_5, sshr_v0_v1_8b_5, 1) +TEST_INPUTS(0) + sshr v0.8b, v1.8b, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_16B, sshr_v0_v1_16b_3, 1) +TEST_INPUTS(0) + sshr v0.16b, v1.16b, #3 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_16B_1, sshr_v0_v1_16b_1, 1) +TEST_INPUTS(0) + sshr v0.16b, v1.16b, #1 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_16B_5, sshr_v0_v1_16b_5, 1) +TEST_INPUTS(0) + sshr v0.16b, v1.16b, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4H, sshr_v0_v1_4h_5, 1) +TEST_INPUTS(0) + sshr v0.4h, v1.4h, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4H_3, sshr_v0_v1_4h_3, 1) +TEST_INPUTS(0) + sshr v0.4h, v1.4h, #3 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4H_11, sshr_v0_v1_4h_11, 1) +TEST_INPUTS(0) + sshr v0.4h, v1.4h, #11 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8H, sshr_v0_v1_8h_5, 1) +TEST_INPUTS(0) + sshr v0.8h, v1.8h, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8H_3, sshr_v0_v1_8h_3, 1) +TEST_INPUTS(0) + sshr v0.8h, v1.8h, #3 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8H_11, sshr_v0_v1_8h_11, 1) +TEST_INPUTS(0) + sshr v0.8h, v1.8h, #11 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2S, sshr_v0_v1_2s_10, 1) +TEST_INPUTS(0) + sshr v0.2s, v1.2s, #10 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2S_5, sshr_v0_v1_2s_5, 1) +TEST_INPUTS(0) + sshr v0.2s, v1.2s, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2S_20, sshr_v0_v1_2s_20, 1) +TEST_INPUTS(0) + sshr v0.2s, v1.2s, #20 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4S, sshr_v0_v1_4s_10, 1) +TEST_INPUTS(0) + sshr v0.4s, v1.4s, #10 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4S_5, sshr_v0_v1_4s_5, 1) +TEST_INPUTS(0) + sshr v0.4s, v1.4s, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4S_20, sshr_v0_v1_4s_20, 1) +TEST_INPUTS(0) + sshr v0.4s, v1.4s, #20 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2D, sshr_v0_v1_2d_20, 1) +TEST_INPUTS(0) + sshr v0.2d, v1.2d, #20 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2D_10, sshr_v0_v1_2d_10, 1) +TEST_INPUTS(0) + sshr v0.2d, v1.2d, #10 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2D_40, sshr_v0_v1_2d_40, 1) +TEST_INPUTS(0) + sshr v0.2d, v1.2d, #40 +TEST_END + +TEST_BEGIN(SSHR_ASISDSHF_R, sshr_d0_d1_20, 1) +TEST_INPUTS(0) + sshr d0, d1, #20 +TEST_END + +TEST_BEGIN(SSHR_ASISDSHF_R_40, sshr_d0_d1_40, 1) +TEST_INPUTS(0) + sshr d0, d1, #40 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8B_INPUTS, sshr_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + sshr v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_16B_INPUTS, sshr_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + sshr v0.16b, v1.16b, #3 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4H_INPUTS, sshr_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + sshr v0.4h, v1.4h, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_8H_INPUTS, sshr_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + sshr v0.8h, v1.8h, #5 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2S_INPUTS, sshr_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + sshr v0.2s, v1.2s, #10 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_4S_INPUTS, sshr_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + sshr v0.4s, v1.4s, #10 +TEST_END + +TEST_BEGIN(SSHR_ASIMDSHF_R_2D_INPUTS, sshr_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + sshr v0.2d, v1.2d, #20 +TEST_END + +TEST_BEGIN(SSHR_ASISDSHF_R_INPUTS, sshr_d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + fmov d1, ARG1_64 + sshr d0, d1, #20 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/SUB_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/SUB_ASIMDSAME_ONLY.S index 139721ff..ed102887 100644 --- a/backend/remill/tests/AArch64/SIMD/SUB_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/SUB_ASIMDSAME_ONLY.S @@ -49,3 +49,73 @@ TEST_BEGIN(SUB_ASIMDSAME_ONLY_2D, sub_v123x2d, 1) TEST_INPUTS(0) sub v0.2d, v1.2d, v2.2d TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_8B_INPUTS, sub_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + sub v0.8b, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_16B_INPUTS, sub_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + sub v0.16b, v1.16b, v2.16b +TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_4H_INPUTS, sub_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + sub v0.4h, v1.4h, v2.4h +TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_8H_INPUTS, sub_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + sub v0.8h, v1.8h, v2.8h +TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_2S_INPUTS, sub_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + sub v0.2s, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_4S_INPUTS, sub_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + sub v0.4s, v1.4s, v2.4s +TEST_END + +TEST_BEGIN(SUB_ASIMDSAME_ONLY_2D_INPUTS, sub_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000002, + 0x8000000000000000, 0x7FFFFFFFFFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + sub v0.2d, v1.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/TBL_ASIMDTBL.S b/backend/remill/tests/AArch64/SIMD/TBL_ASIMDTBL.S new file mode 100644 index 00000000..95ba712e --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/TBL_ASIMDTBL.S @@ -0,0 +1,67 @@ +TEST_BEGIN(TBL_ASIMDTBL_L1_1_8B, tbl_v0_v1_v2_8b_1, 1) +TEST_INPUTS(0) + movi v2.8b, #3 + tbl v0.8b, {v1.16b}, v2.8b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L1_1_8B_V2, tbl_v0_v1_v2_8b_1_v2, 1) +TEST_INPUTS(0) + movi v2.8b, #7 + tbl v0.8b, {v1.16b}, v2.8b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L1_1_16B, tbl_v0_v1_v2_16b_1, 1) +TEST_INPUTS(0) + movi v2.16b, #5 + tbl v0.16b, {v1.16b}, v2.16b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L1_1_16B_V2, tbl_v0_v1_v2_16b_1_v2, 1) +TEST_INPUTS(0) + movi v2.16b, #11 + tbl v0.16b, {v1.16b}, v2.16b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L2_2_8B, tbl_v0_v1v2_v3_8b_2, 1) +TEST_INPUTS(0) + movi v3.8b, #10 + tbl v0.8b, {v1.16b, v2.16b}, v3.8b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L2_2_8B_V2, tbl_v0_v1v2_v3_8b_2_v2, 1) +TEST_INPUTS(0) + movi v3.8b, #15 + tbl v0.8b, {v1.16b, v2.16b}, v3.8b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L2_2_16B, tbl_v0_v1v2_v3_16b_2, 1) +TEST_INPUTS(0) + movi v3.16b, #10 + tbl v0.16b, {v1.16b, v2.16b}, v3.16b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L2_2_16B_V2, tbl_v0_v1v2_v3_16b_2_v2, 1) +TEST_INPUTS(0) + movi v3.16b, #20 + tbl v0.16b, {v1.16b, v2.16b}, v3.16b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L1_1_8B_INPUTS, tbl_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + movi v2.8b, #3 + tbl v0.8b, {v1.16b}, v2.8b +TEST_END + +TEST_BEGIN(TBL_ASIMDTBL_L1_1_16B_INPUTS, tbl_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + movi v2.16b, #5 + tbl v0.16b, {v1.16b}, v2.16b +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UADDL_ASIMDDIFF_L.S b/backend/remill/tests/AArch64/SIMD/UADDL_ASIMDDIFF_L.S new file mode 100644 index 00000000..e8ea98ed --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/UADDL_ASIMDDIFF_L.S @@ -0,0 +1,95 @@ +TEST_BEGIN(UADDL_ASIMDDIFF_L_8H8B, uaddl_v0_v1_v2_8h8b, 1) +TEST_INPUTS(0) + uaddl v0.8h, v1.8b, v2.8b + uaddl v3.8h, v4.8b, v5.8b +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_8H16B, uaddl2_v0_v1_v2_8h16b, 1) +TEST_INPUTS(0) + uaddl2 v0.8h, v1.16b, v2.16b + uaddl2 v3.8h, v4.16b, v5.16b +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_4S4H, uaddl_v0_v1_v2_4s4h, 1) +TEST_INPUTS(0) + uaddl v0.4s, v1.4h, v2.4h + uaddl v3.4s, v4.4h, v5.4h +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_4S8H, uaddl2_v0_v1_v2_4s8h, 1) +TEST_INPUTS(0) + uaddl2 v0.4s, v1.8h, v2.8h + uaddl2 v3.4s, v4.8h, v5.8h +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_2D2S, uaddl_v0_v1_v2_2d2s, 1) +TEST_INPUTS(0) + uaddl v0.2d, v1.2s, v2.2s + uaddl v3.2d, v4.2s, v5.2s +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_2D4S, uaddl2_v0_v1_v2_2d4s, 1) +TEST_INPUTS(0) + uaddl2 v0.2d, v1.4s, v2.4s + uaddl2 v3.2d, v4.4s, v5.4s +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_8H8B_INPUTS, uaddl_v8h8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + uaddl v0.8h, v1.8b, v2.8b +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_8H16B_INPUTS, uaddl2_v8h16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + uaddl2 v0.8h, v1.16b, v2.16b +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_4S4H_INPUTS, uaddl_v4s4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + uaddl v0.4s, v1.4h, v2.4h +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_4S8H_INPUTS, uaddl2_v4s8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + uaddl2 v0.4s, v1.8h, v2.8h +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_2D2S_INPUTS, uaddl_v2d2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + uaddl v0.2d, v1.2s, v2.2s +TEST_END + +TEST_BEGIN(UADDL_ASIMDDIFF_L_2D4S_INPUTS, uaddl2_v2d4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + uaddl2 v0.2d, v1.4s, v2.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UADDW_ASIMDDIFF_W.S b/backend/remill/tests/AArch64/SIMD/UADDW_ASIMDDIFF_W.S new file mode 100644 index 00000000..1647a582 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/UADDW_ASIMDDIFF_W.S @@ -0,0 +1,95 @@ +TEST_BEGIN(UADDW_ASIMDDIFF_W_8H8B, uaddw_v0_v1_v2_8h8b, 1) +TEST_INPUTS(0) + uaddw v0.8h, v1.8h, v2.8b + uaddw v3.8h, v4.8h, v5.8b +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_8H16B, uaddw2_v0_v1_v2_8h16b, 1) +TEST_INPUTS(0) + uaddw2 v0.8h, v1.8h, v2.16b + uaddw2 v3.8h, v4.8h, v5.16b +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_4S4H, uaddw_v0_v1_v2_4s4h, 1) +TEST_INPUTS(0) + uaddw v0.4s, v1.4s, v2.4h + uaddw v3.4s, v4.4s, v5.4h +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_4S8H, uaddw2_v0_v1_v2_4s8h, 1) +TEST_INPUTS(0) + uaddw2 v0.4s, v1.4s, v2.8h + uaddw2 v3.4s, v4.4s, v5.8h +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_2D2S, uaddw_v0_v1_v2_2d2s, 1) +TEST_INPUTS(0) + uaddw v0.2d, v1.2d, v2.2s + uaddw v3.2d, v4.2d, v5.2s +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_2D4S, uaddw2_v0_v1_v2_2d4s, 1) +TEST_INPUTS(0) + uaddw2 v0.2d, v1.2d, v2.4s + uaddw2 v3.2d, v4.2d, v5.4s +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_8H8B_INPUTS, uaddw_v8h8b_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0102030405060708, + 0x8000FFFF7FFF0000, 0x80FF7F0001FE0200, + 0xAAAA5555CCCC3333, 0xAAAAAAAAAAAAAAAA) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + uaddw v0.8h, v1.8h, v2.8b +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_8H16B_INPUTS, uaddw2_v8h16b_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0102030405060708, + 0x8000FFFF7FFF0000, 0x80FF7F0001FE0200, + 0xAAAA5555CCCC3333, 0xAAAAAAAAAAAAAAAA) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + uaddw2 v0.8h, v1.8h, v2.16b +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_4S4H_INPUTS, uaddw_v4s4h_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0001000200030004, + 0x80000000FFFFFFFF, 0x8000FFFF7FFF0000, + 0xAAAAAAAA55555555, 0xAAAA5555CCCC3333) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + uaddw v0.4s, v1.4s, v2.4h +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_4S8H_INPUTS, uaddw2_v4s8h_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0001000200030004, + 0x80000000FFFFFFFF, 0x8000FFFF7FFF0000, + 0xAAAAAAAA55555555, 0xAAAA5555CCCC3333) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + uaddw2 v0.4s, v1.4s, v2.8h +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_2D2S_INPUTS, uaddw_v2d2s_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000100000002, + 0x8000000000000000, 0x80000000FFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0xAAAAAAAA55555555) + dup v1.2d, ARG1_64 + fmov d2, ARG2_64 + uaddw v0.2d, v1.2d, v2.2s +TEST_END + +TEST_BEGIN(UADDW_ASIMDDIFF_W_2D4S_INPUTS, uaddw2_v2d4s_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000100000002, + 0x8000000000000000, 0x80000000FFFFFFFF, + 0xAAAAAAAAAAAAAAAA, 0xAAAAAAAA55555555) + dup v1.2d, ARG1_64 + dup v2.2d, ARG2_64 + uaddw2 v0.2d, v1.2d, v2.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UCVTF_ASIMDMISC_R.S b/backend/remill/tests/AArch64/SIMD/UCVTF_ASIMDMISC_R.S new file mode 100644 index 00000000..f295a8ec --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/UCVTF_ASIMDMISC_R.S @@ -0,0 +1,98 @@ +TEST_BEGIN(UCVTF_ASIMDMISC_R_2S, ucvtf_v0_v1_2s, 1) +TEST_INPUTS(0) + movi v1.2s, #42 + ucvtf v0.2s, v1.2s +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_2S_v2, ucvtf_v3_v4_2s_v2, 1) +TEST_INPUTS(0) + movi v4.2s, #7 + ucvtf v3.2s, v4.2s +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_4S, ucvtf_v0_v1_4s, 1) +TEST_INPUTS(0) + movi v1.4s, #42 + ucvtf v0.4s, v1.4s +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_4S_v2, ucvtf_v3_v4_4s_v2, 1) +TEST_INPUTS(0) + movi v4.4s, #13 + ucvtf v3.4s, v4.4s +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_2D, ucvtf_v0_v1_2d, 1) +TEST_INPUTS(0) + ucvtf v0.2d, v1.2d +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_2D_v2, ucvtf_v3_v4_2d_v2, 1) +TEST_INPUTS(0) + ucvtf v3.2d, v4.2d +TEST_END + +TEST_BEGIN(UCVTF_ASISDMISC_R_32, ucvtf_s0_s1_sisd, 1) +TEST_INPUTS(0) + ucvtf s0, s1 +TEST_END + +TEST_BEGIN(UCVTF_ASISDMISC_R_32_v2, ucvtf_s3_s4_sisd_v2, 1) +TEST_INPUTS(0) + ucvtf s3, s4 +TEST_END + +TEST_BEGIN(UCVTF_ASISDMISC_R_64, ucvtf_d0_d1_sisd, 1) +TEST_INPUTS(0) + ucvtf d0, d1 +TEST_END + +TEST_BEGIN(UCVTF_ASISDMISC_R_64_v2, ucvtf_d3_d4_sisd_v2, 1) +TEST_INPUTS(0) + ucvtf d3, d4 +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_2S_INPUTS, ucvtf_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + ucvtf v0.2s, v1.2s +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_4S_INPUTS, ucvtf_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + ucvtf v0.4s, v1.4s +TEST_END + +TEST_BEGIN(UCVTF_ASIMDMISC_R_2D_INPUTS, ucvtf_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + ucvtf v0.2d, v1.2d +TEST_END + +TEST_BEGIN(UCVTF_ASISDMISC_R_32_INPUTS, ucvtf_s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + ucvtf s0, s1 +TEST_END + +TEST_BEGIN(UCVTF_ASISDMISC_R_64_INPUTS, ucvtf_d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + fmov d1, ARG1_64 + ucvtf d0, d1 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UMAXP_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/UMAXP_ASIMDSAME_ONLY.S index 07cf2435..fef3ee0f 100644 --- a/backend/remill/tests/AArch64/SIMD/UMAXP_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/UMAXP_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) umaxp v6.4s, v2.4s, v3.4s umaxp v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(UMAXP_ASIMDSAME_ONLY_8B_INPUTS, umaxp_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umaxp v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(UMAXP_ASIMDSAME_ONLY_16B_INPUTS, umaxp_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umaxp v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(UMAXP_ASIMDSAME_ONLY_4H_INPUTS, umaxp_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umaxp v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(UMAXP_ASIMDSAME_ONLY_8H_INPUTS, umaxp_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umaxp v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(UMAXP_ASIMDSAME_ONLY_2S_INPUTS, umaxp_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umaxp v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(UMAXP_ASIMDSAME_ONLY_4S_INPUTS, umaxp_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umaxp v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UMAXV_ASIMDALL_ONLY.S b/backend/remill/tests/AArch64/SIMD/UMAXV_ASIMDALL_ONLY.S index 2ad6f928..41bb7a8d 100644 --- a/backend/remill/tests/AArch64/SIMD/UMAXV_ASIMDALL_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/UMAXV_ASIMDALL_ONLY.S @@ -53,3 +53,48 @@ TEST_INPUTS(0) umaxv s7, v2.4s umaxv s8, v3.4s TEST_END + +TEST_BEGIN(UMAXV_ASIMDALL_ONLY_8B_INPUTS, umaxv_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + umaxv b0, v1.8b +TEST_END + +TEST_BEGIN(UMAXV_ASIMDALL_ONLY_16B_INPUTS, umaxv_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + umaxv b0, v1.16b +TEST_END + +TEST_BEGIN(UMAXV_ASIMDALL_ONLY_4H_INPUTS, umaxv_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + umaxv h0, v1.4h +TEST_END + +TEST_BEGIN(UMAXV_ASIMDALL_ONLY_8H_INPUTS, umaxv_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + umaxv h0, v1.8h +TEST_END + +TEST_BEGIN(UMAXV_ASIMDALL_ONLY_4S_INPUTS, umaxv_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + umaxv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UMAX_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/UMAX_ASIMDSAME_ONLY.S index 69e036aa..d559797e 100644 --- a/backend/remill/tests/AArch64/SIMD/UMAX_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/UMAX_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) umax v6.4s, v2.4s, v3.4s umax v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(UMAX_ASIMDSAME_ONLY_8B_INPUTS, umax_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umax v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(UMAX_ASIMDSAME_ONLY_16B_INPUTS, umax_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umax v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(UMAX_ASIMDSAME_ONLY_4H_INPUTS, umax_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umax v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(UMAX_ASIMDSAME_ONLY_8H_INPUTS, umax_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umax v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(UMAX_ASIMDSAME_ONLY_2S_INPUTS, umax_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umax v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(UMAX_ASIMDSAME_ONLY_4S_INPUTS, umax_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umax v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UMINP_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/UMINP_ASIMDSAME_ONLY.S index 1819fdf4..96d960bb 100644 --- a/backend/remill/tests/AArch64/SIMD/UMINP_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/UMINP_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) uminp v6.4s, v2.4s, v3.4s uminp v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(UMINP_ASIMDSAME_ONLY_8B_INPUTS, uminp_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + uminp v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(UMINP_ASIMDSAME_ONLY_16B_INPUTS, uminp_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + uminp v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(UMINP_ASIMDSAME_ONLY_4H_INPUTS, uminp_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + uminp v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(UMINP_ASIMDSAME_ONLY_8H_INPUTS, uminp_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + uminp v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(UMINP_ASIMDSAME_ONLY_2S_INPUTS, uminp_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + uminp v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(UMINP_ASIMDSAME_ONLY_4S_INPUTS, uminp_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + uminp v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UMINV_ASIMDALL_ONLY.S b/backend/remill/tests/AArch64/SIMD/UMINV_ASIMDALL_ONLY.S index bc1019f1..1b8d1947 100644 --- a/backend/remill/tests/AArch64/SIMD/UMINV_ASIMDALL_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/UMINV_ASIMDALL_ONLY.S @@ -53,3 +53,48 @@ TEST_INPUTS(0) uminv s7, v2.4s uminv s8, v3.4s TEST_END + +TEST_BEGIN(UMINV_ASIMDALL_ONLY_8B_INPUTS, uminv_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + uminv b0, v1.8b +TEST_END + +TEST_BEGIN(UMINV_ASIMDALL_ONLY_16B_INPUTS, uminv_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + uminv b0, v1.16b +TEST_END + +TEST_BEGIN(UMINV_ASIMDALL_ONLY_4H_INPUTS, uminv_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + uminv h0, v1.4h +TEST_END + +TEST_BEGIN(UMINV_ASIMDALL_ONLY_8H_INPUTS, uminv_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + uminv h0, v1.8h +TEST_END + +TEST_BEGIN(UMINV_ASIMDALL_ONLY_4S_INPUTS, uminv_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + uminv s0, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/UMIN_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/UMIN_ASIMDSAME_ONLY.S index c030f651..972c00dc 100644 --- a/backend/remill/tests/AArch64/SIMD/UMIN_ASIMDSAME_ONLY.S +++ b/backend/remill/tests/AArch64/SIMD/UMIN_ASIMDSAME_ONLY.S @@ -57,3 +57,63 @@ TEST_INPUTS(0) umin v6.4s, v2.4s, v3.4s umin v7.4s, v4.4s, v5.4s TEST_END + +TEST_BEGIN(UMIN_ASIMDSAME_ONLY_8B_INPUTS, umin_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umin v5.8b, v0.8b, v1.8b +TEST_END + +TEST_BEGIN(UMIN_ASIMDSAME_ONLY_16B_INPUTS, umin_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0807060504030201, + 0x80FF7F0001FE0200, 0x7F00807FFF01FE02, + 0xAAAAAAAAAAAAAAAA, 0x5555555555555555) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umin v5.16b, v0.16b, v1.16b +TEST_END + +TEST_BEGIN(UMIN_ASIMDSAME_ONLY_4H_INPUTS, umin_v4h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umin v5.4h, v0.4h, v1.4h +TEST_END + +TEST_BEGIN(UMIN_ASIMDSAME_ONLY_8H_INPUTS, umin_v8h_inputs, 2) +TEST_INPUTS( + 0x0001000200030004, 0x0004000300020001, + 0x8000FFFF7FFF0000, 0x7FFF000080000001, + 0xAAAA5555CCCC3333, 0x5555AAAA3333CCCC) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umin v5.8h, v0.8h, v1.8h +TEST_END + +TEST_BEGIN(UMIN_ASIMDSAME_ONLY_2S_INPUTS, umin_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + fmov d0, ARG1_64 + fmov d1, ARG2_64 + umin v5.2s, v0.2s, v1.2s +TEST_END + +TEST_BEGIN(UMIN_ASIMDSAME_ONLY_4S_INPUTS, umin_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000100000002, 0x0000000200000001, + 0x80000000FFFFFFFF, 0x7FFFFFFF00000001, + 0xAAAAAAAA55555555, 0x55555555AAAAAAAA) + dup v0.2d, ARG1_64 + dup v1.2d, ARG2_64 + umin v5.4s, v0.4s, v1.4s +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/USHLL_ASIMDSHF_L.S b/backend/remill/tests/AArch64/SIMD/USHLL_ASIMDSHF_L.S new file mode 100644 index 00000000..c0f8f45a --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/USHLL_ASIMDSHF_L.S @@ -0,0 +1,89 @@ +TEST_BEGIN(USHLL_ASIMDSHF_L_8H8B, ushll_v0_v1_8h8b, 1) +TEST_INPUTS(0) + ushll v0.8h, v1.8b, #2 + ushll v3.8h, v4.8b, #5 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_8H16B, ushll2_v0_v1_8h16b, 1) +TEST_INPUTS(0) + ushll2 v0.8h, v1.16b, #2 + ushll2 v3.8h, v4.16b, #5 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_4S4H, ushll_v0_v1_4s4h, 1) +TEST_INPUTS(0) + ushll v0.4s, v1.4h, #3 + ushll v3.4s, v4.4h, #3 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_4S8H, ushll2_v0_v1_4s8h, 1) +TEST_INPUTS(0) + ushll2 v0.4s, v1.8h, #3 + ushll2 v3.4s, v4.8h, #3 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_2D2S, ushll_v0_v1_2d2s, 1) +TEST_INPUTS(0) + ushll v0.2d, v1.2s, #5 + ushll v3.2d, v4.2s, #5 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_2D4S, ushll2_v0_v1_2d4s, 1) +TEST_INPUTS(0) + ushll2 v0.2d, v1.4s, #5 + ushll2 v3.2d, v4.4s, #5 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_8H8B_INPUTS, ushll_8h8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + ushll v0.8h, v1.8b, #2 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_8H16B_INPUTS, ushll2_8h16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + ushll2 v0.8h, v1.16b, #2 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_4S4H_INPUTS, ushll_4s4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + ushll v0.4s, v1.4h, #3 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_4S8H_INPUTS, ushll2_4s8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + ushll2 v0.4s, v1.8h, #3 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_2D2S_INPUTS, ushll_2d2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + ushll v0.2d, v1.2s, #5 +TEST_END + +TEST_BEGIN(USHLL_ASIMDSHF_L_2D4S_INPUTS, ushll2_2d4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + ushll2 v0.2d, v1.4s, #5 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/USHL_ASIMDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/USHL_ASIMDSAME_ONLY.S new file mode 100644 index 00000000..16dff4e2 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/USHL_ASIMDSAME_ONLY.S @@ -0,0 +1,119 @@ +TEST_BEGIN(USHL_ASIMDSAME_ONLY_8B, ushl_v0_v1_v2_8b, 1) +TEST_INPUTS(0) + movi v2.8b, #2 + ushl v0.8b, v1.8b, v2.8b + ushl v3.8b, v4.8b, v2.8b +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_16B, ushl_v0_v1_v2_16b, 1) +TEST_INPUTS(0) + movi v2.16b, #3 + ushl v0.16b, v1.16b, v2.16b + ushl v3.16b, v4.16b, v2.16b +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_4H, ushl_v0_v1_v2_4h, 1) +TEST_INPUTS(0) + movi v2.4h, #4 + ushl v0.4h, v1.4h, v2.4h + ushl v3.4h, v4.4h, v2.4h +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_8H, ushl_v0_v1_v2_8h, 1) +TEST_INPUTS(0) + movi v2.8h, #5 + ushl v0.8h, v1.8h, v2.8h + ushl v3.8h, v4.8h, v2.8h +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_2S, ushl_v0_v1_v2_2s, 1) +TEST_INPUTS(0) + movi v2.2s, #8 + ushl v0.2s, v1.2s, v2.2s + ushl v3.2s, v4.2s, v2.2s +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_4S, ushl_v0_v1_v2_4s, 1) +TEST_INPUTS(0) + movi v2.4s, #16 + ushl v0.4s, v1.4s, v2.4s + ushl v3.4s, v4.4s, v2.4s +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_2D, ushl_v0_v1_v2_2d, 1) +TEST_INPUTS(0) + mov x2, #12 + dup v2.2d, x2 + ushl v0.2d, v1.2d, v2.2d + ushl v3.2d, v4.2d, v2.2d +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_8B_INPUTS, ushl_v8b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0102030405060708, + 0x80FF7F0001FE0200, 0xFCFDFEFF00010203, + 0xAAAAAAAAAAAAAAAA, 0x0505050505050505) + fmov d0, ARG1_64 + fmov d2, ARG2_64 + ushl v0.8b, v0.8b, v2.8b +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_16B_INPUTS, ushl_v16b_inputs, 2) +TEST_INPUTS( + 0x0102030405060708, 0x0102030405060708, + 0x80FF7F0001FE0200, 0xFCFDFEFF00010203, + 0xAAAAAAAAAAAAAAAA, 0x0505050505050505) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + ushl v0.16b, v0.16b, v2.16b +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_4H_INPUTS, ushl_v4h_inputs, 2) +TEST_INPUTS( + 0x0001800000017FFF, 0x0003000300030003, + 0xFFFF000000010002, 0xFFFDFFFD00050005, + 0x8000FFFF7FFF0001, 0x000F000F000F000F) + fmov d0, ARG1_64 + fmov d2, ARG2_64 + ushl v0.4h, v0.4h, v2.4h +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_8H_INPUTS, ushl_v8h_inputs, 2) +TEST_INPUTS( + 0x0001800000017FFF, 0x0003000300030003, + 0xFFFF000000010002, 0xFFFDFFFD00050005, + 0x8000FFFF7FFF0001, 0x000F000F000F000F) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + ushl v0.8h, v0.8h, v2.8h +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_2S_INPUTS, ushl_v2s_inputs, 2) +TEST_INPUTS( + 0x0000000180000000, 0x0000000400000004, + 0xFFFFFFFF00000001, 0xFFFFFFFC00000008, + 0x7FFFFFFF80000001, 0x0000001000000010) + fmov d0, ARG1_64 + fmov d2, ARG2_64 + ushl v0.2s, v0.2s, v2.2s +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_4S_INPUTS, ushl_v4s_inputs, 2) +TEST_INPUTS( + 0x0000000180000000, 0x0000000400000004, + 0xFFFFFFFF00000001, 0xFFFFFFFC00000008, + 0x7FFFFFFF80000001, 0x0000001000000010) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + ushl v0.4s, v0.4s, v2.4s +TEST_END + +TEST_BEGIN(USHL_ASIMDSAME_ONLY_2D_INPUTS, ushl_v2d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000005, + 0x8000000000000000, 0xFFFFFFFFFFFFFFF0, + 0xFFFFFFFFFFFFFFFF, 0x0000000000000020) + dup v0.2d, ARG1_64 + dup v2.2d, ARG2_64 + ushl v0.2d, v0.2d, v2.2d +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/USHL_ASISDSAME_ONLY.S b/backend/remill/tests/AArch64/SIMD/USHL_ASISDSAME_ONLY.S new file mode 100644 index 00000000..e4974f0e --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/USHL_ASISDSAME_ONLY.S @@ -0,0 +1,37 @@ +TEST_BEGIN(USHL_ASISDSAME_ONLY, ushl_d0_d1_d2, 1) +TEST_INPUTS(0) + mov x2, #3 + fmov d2, x2 + ushl d0, d1, d2 +TEST_END + +TEST_BEGIN(USHL_ASISDSAME_ONLY_NEG, ushl_d0_d1_d2_neg, 1) +TEST_INPUTS(0) + mov x2, #-4 + fmov d2, x2 + ushl d0, d1, d2 +TEST_END + +TEST_BEGIN(USHL_ASISDSAME_ONLY_ZERO, ushl_d0_d1_d2_zero, 1) +TEST_INPUTS(0) + mov x2, #0 + fmov d2, x2 + ushl d0, d1, d2 +TEST_END + +TEST_BEGIN(USHL_ASISDSAME_ONLY_LARGE, ushl_d0_d1_d2_large, 1) +TEST_INPUTS(0) + mov x2, #48 + fmov d2, x2 + ushl d0, d1, d2 +TEST_END + +TEST_BEGIN(USHL_ASISDSAME_ONLY_INPUTS, ushl_d_inputs, 2) +TEST_INPUTS( + 0x0000000000000001, 0x0000000000000003, + 0x8000000000000000, 0xFFFFFFFFFFFFFFFC, + 0xFFFFFFFFFFFFFFFF, 0x0000000000000000) + fmov d1, ARG1_64 + fmov d2, ARG2_64 + ushl d0, d1, d2 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/USHR_ASIMDSHF_R.S b/backend/remill/tests/AArch64/SIMD/USHR_ASIMDSHF_R.S new file mode 100644 index 00000000..be5a5779 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/USHR_ASIMDSHF_R.S @@ -0,0 +1,167 @@ +TEST_BEGIN(USHR_ASIMDSHF_R_8B, ushr_v0_v1_8b_3, 1) +TEST_INPUTS(0) + ushr v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8B_1, ushr_v0_v1_8b_1, 1) +TEST_INPUTS(0) + ushr v0.8b, v1.8b, #1 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8B_5, ushr_v0_v1_8b_5, 1) +TEST_INPUTS(0) + ushr v0.8b, v1.8b, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_16B, ushr_v0_v1_16b_3, 1) +TEST_INPUTS(0) + ushr v0.16b, v1.16b, #3 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_16B_1, ushr_v0_v1_16b_1, 1) +TEST_INPUTS(0) + ushr v0.16b, v1.16b, #1 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_16B_5, ushr_v0_v1_16b_5, 1) +TEST_INPUTS(0) + ushr v0.16b, v1.16b, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4H, ushr_v0_v1_4h_5, 1) +TEST_INPUTS(0) + ushr v0.4h, v1.4h, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4H_3, ushr_v0_v1_4h_3, 1) +TEST_INPUTS(0) + ushr v0.4h, v1.4h, #3 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4H_11, ushr_v0_v1_4h_11, 1) +TEST_INPUTS(0) + ushr v0.4h, v1.4h, #11 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8H, ushr_v0_v1_8h_5, 1) +TEST_INPUTS(0) + ushr v0.8h, v1.8h, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8H_3, ushr_v0_v1_8h_3, 1) +TEST_INPUTS(0) + ushr v0.8h, v1.8h, #3 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8H_11, ushr_v0_v1_8h_11, 1) +TEST_INPUTS(0) + ushr v0.8h, v1.8h, #11 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2S, ushr_v0_v1_2s_10, 1) +TEST_INPUTS(0) + ushr v0.2s, v1.2s, #10 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2S_5, ushr_v0_v1_2s_5, 1) +TEST_INPUTS(0) + ushr v0.2s, v1.2s, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2S_20, ushr_v0_v1_2s_20, 1) +TEST_INPUTS(0) + ushr v0.2s, v1.2s, #20 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4S, ushr_v0_v1_4s_10, 1) +TEST_INPUTS(0) + ushr v0.4s, v1.4s, #10 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4S_5, ushr_v0_v1_4s_5, 1) +TEST_INPUTS(0) + ushr v0.4s, v1.4s, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4S_20, ushr_v0_v1_4s_20, 1) +TEST_INPUTS(0) + ushr v0.4s, v1.4s, #20 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2D, ushr_v0_v1_2d_20, 1) +TEST_INPUTS(0) + ushr v0.2d, v1.2d, #20 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2D_10, ushr_v0_v1_2d_10, 1) +TEST_INPUTS(0) + ushr v0.2d, v1.2d, #10 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2D_40, ushr_v0_v1_2d_40, 1) +TEST_INPUTS(0) + ushr v0.2d, v1.2d, #40 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8B_INPUTS, ushr_v8b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + fmov d1, ARG1_64 + ushr v0.8b, v1.8b, #3 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_16B_INPUTS, ushr_v16b_inputs, 1) +TEST_INPUTS( + 0x0102040810204080, + 0xFF00FF00FF00FF00, + 0x80817F7E01020304) + dup v1.2d, ARG1_64 + ushr v0.16b, v1.16b, #3 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4H_INPUTS, ushr_v4h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + fmov d1, ARG1_64 + ushr v0.4h, v1.4h, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_8H_INPUTS, ushr_v8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + ushr v0.8h, v1.8h, #5 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2S_INPUTS, ushr_v2s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + fmov d1, ARG1_64 + ushr v0.2s, v1.2s, #10 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_4S_INPUTS, ushr_v4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + ushr v0.4s, v1.4s, #10 +TEST_END + +TEST_BEGIN(USHR_ASIMDSHF_R_2D_INPUTS, ushr_v2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + ushr v0.2d, v1.2d, #20 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/USHR_ASISDSHF_R.S b/backend/remill/tests/AArch64/SIMD/USHR_ASISDSHF_R.S index 9aa760dd..2084a4c2 100644 --- a/backend/remill/tests/AArch64/SIMD/USHR_ASISDSHF_R.S +++ b/backend/remill/tests/AArch64/SIMD/USHR_ASISDSHF_R.S @@ -20,3 +20,12 @@ TEST_INPUTS(0) ushr d6, d7, #2 ushr d7, d8, #3 TEST_END + +TEST_BEGIN(USHR_ASISDSHF_R_INPUTS, ushr_d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + fmov d6, ARG1_64 + ushr d5, d6, #2 +TEST_END diff --git a/backend/remill/tests/AArch64/SIMD/XTN_ASIMDMISC_N.S b/backend/remill/tests/AArch64/SIMD/XTN_ASIMDMISC_N.S new file mode 100644 index 00000000..f8574040 --- /dev/null +++ b/backend/remill/tests/AArch64/SIMD/XTN_ASIMDMISC_N.S @@ -0,0 +1,89 @@ +TEST_BEGIN(XTN_ASIMDMISC_N_8B8H, xtn_v0_v1_8b8h, 1) +TEST_INPUTS(0) + xtn v0.8b, v1.8h + xtn v3.8b, v4.8h +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_16B8H, xtn2_v0_v1_16b8h, 1) +TEST_INPUTS(0) + xtn2 v0.16b, v1.8h + xtn2 v3.16b, v4.8h +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_4H4S, xtn_v0_v1_4h4s, 1) +TEST_INPUTS(0) + xtn v0.4h, v1.4s + xtn v3.4h, v4.4s +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_8H4S, xtn2_v0_v1_8h4s, 1) +TEST_INPUTS(0) + xtn2 v0.8h, v1.4s + xtn2 v3.8h, v4.4s +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_2S2D, xtn_v0_v1_2s2d, 1) +TEST_INPUTS(0) + xtn v0.2s, v1.2d + xtn v3.2s, v4.2d +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_4S2D, xtn2_v0_v1_4s2d, 1) +TEST_INPUTS(0) + xtn2 v0.4s, v1.2d + xtn2 v3.4s, v4.2d +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_8B8H_INPUTS, xtn_8b8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + xtn v0.8b, v1.8h +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_16B8H_INPUTS, xtn2_16b8h_inputs, 1) +TEST_INPUTS( + 0x0001800000017FFF, + 0xFFFF000000010002, + 0x8000FFFF7FFF0001) + dup v1.2d, ARG1_64 + xtn2 v0.16b, v1.8h +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_4H4S_INPUTS, xtn_4h4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + xtn v0.4h, v1.4s +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_8H4S_INPUTS, xtn2_8h4s_inputs, 1) +TEST_INPUTS( + 0x0000000180000000, + 0xFFFFFFFF00000001, + 0x7FFFFFFF80000001) + dup v1.2d, ARG1_64 + xtn2 v0.8h, v1.4s +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_2S2D_INPUTS, xtn_2s2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + xtn v0.2s, v1.2d +TEST_END + +TEST_BEGIN(XTN_ASIMDMISC_N_4S2D_INPUTS, xtn2_4s2d_inputs, 1) +TEST_INPUTS( + 0x0000000000000001, + 0x8000000000000000, + 0xFFFFFFFFFFFFFFFF) + dup v1.2d, ARG1_64 + xtn2 v0.4s, v1.2d +TEST_END diff --git a/backend/remill/tests/AArch64/Tests.S b/backend/remill/tests/AArch64/Tests.S index 77a8b655..3f7a33b0 100644 --- a/backend/remill/tests/AArch64/Tests.S +++ b/backend/remill/tests/AArch64/Tests.S @@ -289,8 +289,16 @@ SYMBOL(__aarch64_test_table_begin): #include "tests/AArch64/BINARY/FABS_t_FLOATDP1.S" #include "tests/AArch64/BINARY/FNEG_t_FLOATDP1.S" #include "tests/AArch64/BINARY/FMADD_t_FLOATDP3.S" +#include "tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S" +#include "tests/AArch64/BINARY/FNMSUB_t_FLOATDP3.S" +#include "tests/AArch64/BINARY/FMAX_t_FLOATDP2.S" +#include "tests/AArch64/BINARY/FSQRT_t_FLOATDP1.S" +#include "tests/AArch64/BINARY/UMSUBL_64WA_DP_3SRC.S" +#include "tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S" +#include "tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S" #include "tests/AArch64/BITBYTE/BFM_nM_BITFIELD.S" +#include "tests/AArch64/BITBYTE/CLS_n_DP_1SRC.S" #include "tests/AArch64/BITBYTE/CLZ_n_DP_1SRC.S" #include "tests/AArch64/BITBYTE/EXTR_n_EXTRACT.S" #include "tests/AArch64/BITBYTE/RBIT.S" @@ -308,6 +316,12 @@ SYMBOL(__aarch64_test_table_begin): #include "tests/AArch64/CONVERT/FCVT_t_FLOAT2INT.S" #include "tests/AArch64/CONVERT/SCVTF_n_FLOAT2INT.S" #include "tests/AArch64/CONVERT/UCVTF_n_FLOAT2INT.S" +// TODO: FCVTAS semantics bug - lifted result differs from native +// #include "tests/AArch64/CONVERT/FCVTAS_nS_FLOAT2INT.S" +#include "tests/AArch64/CONVERT/FCVTZS_64S_FLOAT2INT.S" +// TODO: FRINTA semantics bug - lifted result differs from native +// #include "tests/AArch64/CONVERT/FRINTA_t_FLOATDP1.S" +#include "tests/AArch64/CONVERT/FRINTM_t_FLOATDP1.S" #include "tests/AArch64/DATAXFER/FMOV_t_FLOATIMM.S" #include "tests/AArch64/DATAXFER/FMOV_NToN.S" @@ -362,6 +376,17 @@ SYMBOL(__aarch64_test_table_begin): #include "tests/AArch64/DATAXFER/STUR_n_LDST_UNSCALED.S" #include "tests/AArch64/DATAXFER/UMOV.S" #include "tests/AArch64/DATAXFER/INS_ASIMDINS_IR_R.S" +#include "tests/AArch64/DATAXFER/MOVN_n_MOVEWIDE.S" +#include "tests/AArch64/DATAXFER/STUR_FP_LDST_UNSCALED.S" +#include "tests/AArch64/DATAXFER/LDUR_FP_LDST_UNSCALED.S" +#include "tests/AArch64/DATAXFER/LD1R_ASISDLSO_R1.S" +// TODO: LD1/ST1 single-structure lifter crash - memory operand type mismatch +// #include "tests/AArch64/DATAXFER/LD1_ASISDLSO_SINGLE.S" +// #include "tests/AArch64/DATAXFER/LD1_ASISDLSOP_SINGLE.S" +// #include "tests/AArch64/DATAXFER/ST1_ASISDLSO_SINGLE.S" +// #include "tests/AArch64/DATAXFER/ST1_ASISDLSOP_SINGLE.S" +#include "tests/AArch64/DATAXFER/STP_FP_LDSTPAIR.S" +#include "tests/AArch64/DATAXFER/STR_FP_LDST.S" #include "tests/AArch64/LOGICAL/AND_n_LOG_IMM.S" #include "tests/AArch64/LOGICAL/AND_n_LOG_SHIFT.S" @@ -375,6 +400,10 @@ SYMBOL(__aarch64_test_table_begin): #include "tests/AArch64/LOGICAL/ORN_n_LOG_SHIFT.S" #include "tests/AArch64/LOGICAL/ORR_n_LOG_IMM.S" #include "tests/AArch64/LOGICAL/ORR_n_LOG_SHIFT.S" +#include "tests/AArch64/LOGICAL/LSLV_n_DP_2SRC.S" +#include "tests/AArch64/LOGICAL/LSRV_n_DP_2SRC.S" +#include "tests/AArch64/LOGICAL/ASRV_n_DP_2SRC.S" +#include "tests/AArch64/LOGICAL/RORV_n_DP_2SRC.S" #include "tests/AArch64/MISC/NOP.S" @@ -393,6 +422,7 @@ SYMBOL(__aarch64_test_table_begin): #include "tests/AArch64/SIMD/BIT_ASIMDSAME_ONLY.S" #include "tests/AArch64/SIMD/BSL_ASIMDSAME_ONLY.S" #include "tests/AArch64/SIMD/CMcc_ASIMDMISC_Z.S" +#include "tests/AArch64/SIMD/CMGE_ASISDMISC_Z.S" #include "tests/AArch64/SIMD/CMcc_ASIMDSAME_ONLY.S" #include "tests/AArch64/SIMD/DUP_ASIMDINS_DR_R.S" #include "tests/AArch64/SIMD/EOR_ASIMDSAME_ONLY.S" @@ -416,7 +446,45 @@ SYMBOL(__aarch64_test_table_begin): // #include "tests/AArch64/SIMD/NOT_ASIMDMISC_R.S" #include "tests/AArch64/SIMD/EXT_ASIMDINS_ONLY.S" // #include "tests/AArch64/SIMD/USHR_ASISDSHF_R.S" - +#include "tests/AArch64/SIMD/AND_ASIMDSAME_ONLY.S" +#include "tests/AArch64/SIMD/BIC_ASIMDIMM_L.S" +#include "tests/AArch64/SIMD/CMLE_ASIMDMISC_Z.S" +#include "tests/AArch64/SIMD/CMLT_ASIMDMISC_Z.S" +#include "tests/AArch64/SIMD/CMHS_ASIMDSAME_ONLY.S" +#include "tests/AArch64/SIMD/CMTST_ASIMDSAME_ONLY.S" +#include "tests/AArch64/SIMD/CNT_ASIMDMISC_R.S" +#include "tests/AArch64/SIMD/REV32_ASIMDMISC_R.S" +#include "tests/AArch64/SIMD/SSHL_ASIMDSAME_ONLY.S" +#include "tests/AArch64/SIMD/USHL_ASIMDSAME_ONLY.S" +#include "tests/AArch64/SIMD/USHL_ASISDSAME_ONLY.S" +#include "tests/AArch64/SIMD/SHL_ASIMDSHF_R.S" +#include "tests/AArch64/SIMD/SSHR_ASIMDSHF_R.S" +#include "tests/AArch64/SIMD/USHR_ASIMDSHF_R.S" +#include "tests/AArch64/SIMD/SSHLL_ASIMDSHF_L.S" +#include "tests/AArch64/SIMD/USHLL_ASIMDSHF_L.S" +#include "tests/AArch64/SIMD/SHLL_ASIMDMISC_S.S" +#include "tests/AArch64/SIMD/XTN_ASIMDMISC_N.S" +#include "tests/AArch64/SIMD/SADDW_ASIMDDIFF_W.S" +#include "tests/AArch64/SIMD/UADDL_ASIMDDIFF_L.S" +#include "tests/AArch64/SIMD/UADDW_ASIMDDIFF_W.S" +#include "tests/AArch64/SIMD/TBL_ASIMDTBL.S" +#include "tests/AArch64/SIMD/ADDP_ASISDPAIR_ONLY.S" +#include "tests/AArch64/SIMD/DUP_ASIMDINS_DV_V.S" +// TODO: DUP scalar semantics bug - upper bits not zeroed +// #include "tests/AArch64/SIMD/DUP_ASISDONE_ONLY.S" +#include "tests/AArch64/SIMD/INS_ASIMDINS_IV_V.S" +// TODO: SIMD FP arithmetic tests crash the test runner +// #include "tests/AArch64/SIMD/FADD_ASIMDSAME_ONLY.S" +// #include "tests/AArch64/SIMD/FSUB_ASIMDSAME_ONLY.S" +// #include "tests/AArch64/SIMD/FMUL_ASIMDSAME_ONLY.S" +// #include "tests/AArch64/SIMD/FDIV_ASIMDSAME_ONLY.S" +// #include "tests/AArch64/SIMD/FMLA_ASIMDSAME_ONLY.S" +// #include "tests/AArch64/SIMD/FMLA_ASIMDELEM_R_SD.S" +// #include "tests/AArch64/SIMD/FMUL_ASIMDELEM_R_SD.S" +// #include "tests/AArch64/SIMD/FRINTM_ASIMDMISC_R.S" +// #include "tests/AArch64/SIMD/SCVTF_ASIMDMISC_R.S" +// #include "tests/AArch64/SIMD/UCVTF_ASIMDMISC_R.S" +// #include "tests/AArch64/SIMD/FCVTZU_ASISDMISC_R.S" #include "tests/AArch64/SYSTEM/Mn_n_SYSTEM_FPSR.S" #include "tests/AArch64/SYSTEM/Mn_n_SYSTEM_FPCR.S"