SystemVerilog support#44

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robtaylor wants to merge 35 commits intomainfrom

verilog-support

Commits on Jan 13, 2026

Update gitignore
robtaylor
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Start of experiment with toml binding of verilog/generated verilog
robtaylor
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Sort out typing
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wip: verilog binding
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More typing
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mergeme: typing
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wip: more autobinding
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feat: complete TOML-based Verilog wrapper system

claude
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robtaylor
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feat: add SystemVerilog support with sv2v conversion

claude
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robtaylor
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feat: add SoftwareDriverSignature and port direction support

claude
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robtaylor
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feat: add auto-mapping for well-known interfaces

claude
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robtaylor
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refactor: auto-mapping infers from Verilog signal names

claude
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robtaylor
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feat: add integration tests for wb_timer peripheral

claude
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robtaylor
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feat: add yosys-slang generator for SystemVerilog conversion

claude
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robtaylor
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fix: yowasp-yosys has slang built-in, no plugin loading needed

claude
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robtaylor
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feat: add yowasp-yosys dependency for SystemVerilog support

claude
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robtaylor
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fix: resolve path relative to TOML file, fix tests for yowasp-yosys

claude
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robtaylor
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chore: ignore .python-version file

claude
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robtaylor
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fix: use commit hash instead of branch name for pythondata-misc-usb_ohci
robtaylor
committed

Commits on Jan 16, 2026

Commits on Jan 20, 2026