A RISC-V CPU implementing the RV32I base instruction set, Zicsr extension, and machine mode privileged architecture designed to run on the Lattice ECP5 LFE5U-85 FPGA on the OrangeCrab development board.

Build

There are different example programs to run, each in their own directory. All require, for both simulation and running on hardware:

• A GCC toolchain targeting riscv32
• The latest stable Rust toolchain

Simulation

The CPU can be simulated using verilator. To simulate the CPU with an example program, run make sim from that example program's directory. For example, to simulate the CPU with the blink program, run

make -C blink sim

from the top repository directory.

Running on Hardware

Building and installing to an OrangeCrab development board requires several dependencies:

• yosys - nightly version required
• nextpnr-ecp5 - nightly version required
• dfu-util

On Arch Linux, it is sufficient to install nextpnr-ecp5-nightly from the AUR (it has yosys-nightly as a dependency) and the official dfu-util package

With the OrangeCrab board plugged in via USB, run make sim from an example program's directory. For example, to run the blink program on the hardware, run

make -C blink install

from the top repository directory.

Tests

Tests run as simulations, so running tests has the same requirements as running simulations. Run tests with the test script:

./test.sh