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DigitalLogicSimCommunity / Digital-Logic-Sim-CE Public

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Fork 32
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Scaleclock#76

Open

DHMike57 wants to merge 7 commits intoDigitalLogicSimCommunity:mainDigitalLogicSimCommunity/Digital-Logic-Sim-CE:mainfrom

ml57:scaleclockml57/Digital-Logic-Sim-CE:scaleclockCopy head branch name to clipboard

Conversation Commits7 (7)Checks Files changed

Open

Scaleclock#76
DHMike57 wants to merge 7 commits intoDigitalLogicSimCommunity:mainfrom
ml57:scaleclock

Commits

Commits on Mar 14, 2023

add 7 segment display
DHMike57
committed
merged 7seg and ci
DHMike57
committed

Commits on Mar 18, 2023

7sec scalable, pins off, moved to comp
DHMike57
committed
Merge pull request #1 from DHMike57/sevenseg
DHMike57
authored
Revert "Sevenseg"
DHMike57
authored
Merge pull request #2 from ml57/revert-1-sevenseg
DHMike57
authored

Commits on Mar 19, 2023

add scaling to clock
DHMike57
committed

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