Subsystem: Design Core

**Purpose:** 5-stage RV32IMA core with M/S-mode, interrupts, debug hooks.

**Main File(s)**

- [Core Top](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/rv32_core.sv)

**Sub-Files**
- [Fetch Stage](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/fetch.sv)
- [Decode Stage](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/decode.sv)
- [Execute Stage](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/execute.sv)
- [Memory Stage](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/mem_stage.sv)
- [Writeback Stage](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/writeback.sv)
- [Branch Predictor](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/branch_predictor.sv)
- [CSR File](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/csr_file.sv)
- [Fence Unit](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/fence_unit.sv)
- [Hazard Unit](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/hazard_unit.sv)
- [LR/SC Unit](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/rv32a_lrsc.sv)
- [Mul/Div Unit](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/cpu/core/rv32m_muldiv.sv)

**Related Sub-Issues (Dependencies)**
Cache: #5 
MMU: #22 
Interrupts: #23 

**Co-Lead**
Sebastian Candelaria

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Subsystem: Design Core #13

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Subsystem: Design Core #13

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