PIMLC

Logic Compilation for Processing-in-Memory

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This project provide a compiler to convert high-level Boolean function (written as combinational verilog module) into the the low-level primitives support by bit-serial based processing-in-memory system.

Please cite our work if this project helps your research

@inproceedings{tang2024PIMLC,
  title={PIMLC: Logic Compiler for Bit-serial Based PIM},
  author={Tang, Chenyu and Nie,Chen and Qian, Weikang and He, Zhezhi},
  booktitle={Design, Automation and Test in Europe Conference (DATE)},
  year={2024},
  organization={IEEE}
}

Installation

On Ubuntu 20.04:

sudo apt-get install coinor-cbc=2.8.12-1build2 coinor-libcbc-dev=2.8.12-1build2 # coinor libs for ILP part
git clone --recursive https://github.com/Intelligent-Computing-Research-Group/PIMLC.git
cd PIMLC
make

Run

After installation you can generate logic instructions using: ./bin/codegen ./benchmark/div.v ./config/SRAM.conf 1024 LBCP > test.asm.

• ./bin/codegen is compiled from source code
• ./benchmark/div.v is a divisor module from PIMLC's submodule PIMLC-Benchmark.
• ./config/SRAM.conf is the config file of your PIM.

You can also refer to simulation/simulate.sh to generate performance statistics data.

Doxygen

This repo uses Doxygen to generate documentation from source code.

First, you should edit Doxyfile for further configuration and you can refer to the official manual to find more about the details.

Use doxygen command (you need to install doxygen first) to generate documentation in the html and latex folder. We basically use the web browesr and start with the index.html in html.

Validation and Benchmark

We built a simulator and use existing benchmark to validate the functionality of our PIMLC.

The simulator runs the instructions generated by PIMLC. It compares the results with the output of Verilator.

The benchmark is chosen from EFPL Combinational Benchmark Suite with some modifications. Use git submodule update --init to get the benchmark submodule.

Future Works

• Support reshape in block. Suppose 4 sub-array(256bits X 256bits) forms a mat and a mat works as a block (Atomic SIMD engine). We currently treat the block as a 256bits X 1024bits SIMD engine. But it is possible to make it a 512bits X 512bits or 1024bits X 256bits SIMD engine as well.