Computer Engineering @ Georgia Tech · RTL Design | Design Verification | | Operating Systems | Embedded Systems | Networking | AI/ML | Hardware-Acceleration | GPU Optimization | AI Infrastructure GenAI

I specialize in the intersection of Computer Architecture and System Software. My work focuses on building high-performance hardware-software systems, with a particular interest in:

• Chip Design & Verification: RTL design (SystemVerilog/VHDL), UVM/Formal verification, and physical design workflows.
• Operating Systems & Low-Level: Kernel development, memory management, and hardware-software abstraction (C/C++, Linux).
• Networking & Protocols: Implementing hardware-level communication stacks (TCP/IP, UART, SPI, I2C) and high-speed interconnects.
• Hardware-AI Acceleration: Architecting custom silicon and FPGA accelerators for LLM and GNN workloads.
• Embedded Systems: Real-time signal analysis, bare-metal firmware, and FPGA-based DSP.

Synchronizing-Threads Concurrency & Operating Systems

• Implementation of thread synchronization primitives and multi-threaded coordination.
• Focuses on avoiding deadlocks, race conditions, and optimizing resource sharing in a concurrent environment.

Catching-Caches Computer Architecture & Memory Hierarchy

• Exploration of cache coherence, hit/miss optimization, and memory subsystem performance.
• Demonstrates deep understanding of CPU-to-Memory bottlenecks and architectural efficiency.

ZenOS Operating Systems & Kernel Implementation

• Focuses on process scheduling, virtual memory management, and interrupt handling.
• Exploring hardware abstraction layers and system call implementations in C.

ZeNetwork Communication & Networking

• Implementation of low-level networking stacks and communication protocols.
• Focused on reliability, packet parsing, and low-latency data transmission for embedded environments.

SystemVerilog-64-Bit-Calculator Digital Design & Verification

• A 64-bit ALU/Calculator implementation utilizing a full digital design and physical design methodology.
• Features comprehensive verification testbench and TCL scripting for tool automation.

Sveri-ML Hardware-AI Acceleration (SystemVerilog)

• An open-source library for Machine Learning primitives implemented natively in SystemVerilog.
• Enables FPGA/ASIC prototyping for neural network inference.

GNNs-From-Scratch GPU Optimization & CUDA

• High-performance implementation of Graph Neural Networks using CUDA and C++.
• Focused on bridging ground-level ML theory with hardware-specific optimization.

Kube-AI-Pipeline AI Infrastructure

• GPU-supported pipeline for training and serving models via Docker/Kubernetes.

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Let's build next-generation hardware-software systems.