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Refs/heads/split utage perf #746

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d1b55e7
cpu-o3: split microtage out of tage
Jan 6, 2026
bd6087d
cpu-o3: enhance branch index calculation in MicroTAGE to handle edge …
Jan 6, 2026
542f6cb
cpu-o3: update blockWidth calculation to handle zero blockSize
Jan 6, 2026
c23b9a9
cpu-o3: adjust MicroTAGE parameters and clean up code for clarity
Jan 8, 2026
a358334
cpu-o3: remove unused variable 'usingBasetable'
Jan 8, 2026
9a01469
cpu-o3: MicroTAGE to remove base table and alternative prediction
Jan 9, 2026
05a0f32
cpu-o3: update MicroTAGE parameters for consistency
Jan 9, 2026
bfb1563
cpu-o3: remove alternative prediction logic
Jan 12, 2026
f742b1b
cpu-o3: refine MicroTAGE parameters and remove unused variables
Jan 13, 2026
9404558
cpu-o3: update MicroTAGE history length parameter to 16
Jan 13, 2026
7a5d5ab
cpu-o3: enhance MicroTAGE history management with ahead queues
Jan 14, 2026
042d451
cpu-o3:open microtage
Jan 15, 2026
7e25f61
cpu-o3:close utage in ideal
Jan 15, 2026
aeff5ff
cpu-o3: update folded history queue size limit
Jan 23, 2026
63be8d5
cpu-o3: disable MicroTAGE in branch prediction configuration
Jan 23, 2026
50728be
cpu-o3: refine folded history queue management in doUpdateHist
Jan 23, 2026
ba883a1
cpu-o3: update .gitignore and modify MicroTAGE predictor includes
Jan 28, 2026
add8efc
cpu-o3: refactor MicroTAGE history management by removing ahead index…
Jan 28, 2026
313a558
cpu-o3: enhance MicroTAGE predictor with alternative tag handling and…
Jan 29, 2026
e3cc980
cpu-o3:change utage to s1
Jan 30, 2026
11dd8a5
cpu-o3: update prediction latency to zero in MicroTAGE predictor
Jan 30, 2026
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1 change: 1 addition & 0 deletions configs/example/idealkmhv3.py
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Expand Up @@ -80,6 +80,7 @@ def setKmhV3IdealParams(args, system):
if args.bp_type == 'DecoupledBPUWithBTB':
cpu.branchPred.ftq_size = 256
cpu.branchPred.fsq_size = 256
# cpu.branchPred.microtage.enabled = False

# l1 cache per core
if args.caches:
Expand Down
2 changes: 1 addition & 1 deletion configs/example/kmhv3.py
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Expand Up @@ -101,7 +101,7 @@ def setKmhV3Params(args, system):

cpu.branchPred.ubtb.enabled = True
cpu.branchPred.abtb.enabled = True
cpu.branchPred.microtage.enabled = False
cpu.branchPred.microtage.enabled = True
cpu.branchPred.mbtb.enabled = True
cpu.branchPred.tage.enabled = True
cpu.branchPred.ittage.enabled = True
Expand Down
39 changes: 28 additions & 11 deletions src/cpu/pred/BranchPredictor.py
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Expand Up @@ -1060,16 +1060,33 @@ class BTBTAGE(TimedBaseBTBPredictor):
enableBankConflict = Param.Bool(True, "Enable bank conflict simulation")
numDelay = 2

class MicroTAGE(BTBTAGE):
"""A smaller TAGE predictor configuration to assist uBTB"""
enableSC = Param.Bool(False, "Enable SC or not") # TODO: BTBTAGE doesn't support SC
numPredictors = 1
tableSizes = [512]
TTagBitSizes = [16]
TTagPcShifts = [1]

histLengths = [16]
numDelay = 0
class MicroTAGE(TimedBaseBTBPredictor):
"""Micro-sized BTB TAGE predictor used alongside uBTB"""
type = 'MicroTAGE'
cxx_class = 'gem5::branch_prediction::btb_pred::MicroTAGE'
cxx_header = "cpu/pred/btb/microtage.hh"

needMoreHistories = Param.Bool(True, "MicroTAGE needs more histories")
enableSC = Param.Bool(False, "Enable SC or not")
updateOnRead = Param.Bool(True,"Enable update on read, no need to save tage meta in FTQ")
# Keep vector parameters consistent with numPredictors to avoid constructor asserts.
numPredictors = Param.Unsigned(1, "Number of TAGE predictors")
tableSizes = VectorParam.Unsigned([512],"the TAGE T0~Tn length")
TTagBitSizes = VectorParam.Unsigned([16] ,"the T0~Tn entry's tag bit size")
TTagPcShifts = VectorParam.Unsigned([1] ,"when the T0~Tn entry's tag generating, PC right shift")
blockSize = Param.Unsigned(32,"tage index function uses 32B aligned block address")

histLengths = VectorParam.Unsigned([16],"the BTB TAGE T0~Tn history length")
maxHistLen = Param.Unsigned(970,"The length of history passed from DBP")
numTablesToAlloc = Param.Unsigned(1,"The number of table to allocated each time")
numWays = Param.Unsigned(2, "Number of ways per set")
baseTableSize = Param.Unsigned(256,"Base table size")
maxBranchPositions = Param.Unsigned(32,"Maximum branch positions per 64-byte block")
useAltOnNaSize = Param.Unsigned(128,"Size of the useAltOnNa table")
useAltOnNaWidth = Param.Unsigned(7,"Width of the useAltOnNa table")
numBanks = Param.Unsigned(4,"Number of banks for bank conflict simulation")
enableBankConflict = Param.Bool(False,"Enable bank conflict simulation")
numDelay = Param.Unsigned(0,"Prediction latency in cycles")
Comment on lines +1063 to +1089
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⚠️ Potential issue | 🟠 Major

🧩 Analysis chain

🏁 Script executed:

#!/bin/bash
# Search for baseTableSize usage in the codebase
echo "=== Searching for baseTableSize in all files ==="
rg -n 'baseTableSize' --type cpp --type-add 'cpp:*.cc' --type-add 'cpp:*.hh' 2>/dev/null || echo "No matches found"

echo ""
echo "=== Looking for microtage files ==="
fd -e 'cc' -e 'hh' | grep -i microtage

echo ""
echo "=== Searching for p.baseTableSize pattern ==="
rg -n 'p\.baseTableSize' 2>/dev/null || echo "No matches found"

Repository: OpenXiangShan/GEM5

Length of output: 524

🏁 Script executed:

#!/bin/bash
# Check the MicroTAGE constructor to see what parameters are actually consumed
echo "=== Searching for MicroTAGE constructor in microtage.cc ==="
rg -A 80 'MicroTAGE::MicroTAGE' src/cpu/pred/btb/microtage.cc | head -100

echo ""
echo "=== Checking which p. parameters are accessed in microtage.cc ==="
rg -n 'p\.' src/cpu/pred/btb/microtage.cc | head -20

Repository: OpenXiangShan/GEM5

Length of output: 4409

Remove unused parameters from MicroTAGE configuration.

The C++ constructor uses only a subset of the declared parameters. The following parameters are not accessed in the MicroTAGE implementation and should be removed from the Python configuration:

  • baseTableSize (line 1083)
  • enableSC (line 1070)
  • useAltOnNaSize (line 1086)
  • useAltOnNaWidth (line 1087)

These appear to be copy-pasted from other predictor classes (likely BTBTAGE) but are not integrated into MicroTAGE's C++ implementation. The actual constructor parameters used are: numPredictors, tableSizes, TTagBitSizes, TTagPcShifts, histLengths, maxHistLen, numWays, maxBranchPositions, numTablesToAlloc, updateOnRead, numBanks, blockSize, enableBankConflict, and needMoreHistories.

🧰 Tools
🪛 Ruff (0.14.14)

[error] 1069-1069: Param may be undefined, or defined from star imports

(F405)

[error] 1070-1070: Param may be undefined, or defined from star imports

(F405)

[error] 1071-1071: Param may be undefined, or defined from star imports

(F405)

[error] 1073-1073: Param may be undefined, or defined from star imports

(F405)

[error] 1074-1074: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1075-1075: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1076-1076: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1077-1077: Param may be undefined, or defined from star imports

(F405)

[error] 1079-1079: VectorParam may be undefined, or defined from star imports

(F405)

[error] 1080-1080: Param may be undefined, or defined from star imports

(F405)

[error] 1081-1081: Param may be undefined, or defined from star imports

(F405)

[error] 1082-1082: Param may be undefined, or defined from star imports

(F405)

[error] 1083-1083: Param may be undefined, or defined from star imports

(F405)

[error] 1084-1084: Param may be undefined, or defined from star imports

(F405)

[error] 1085-1085: Param may be undefined, or defined from star imports

(F405)

[error] 1086-1086: Param may be undefined, or defined from star imports

(F405)

[error] 1087-1087: Param may be undefined, or defined from star imports

(F405)

[error] 1088-1088: Param may be undefined, or defined from star imports

(F405)

[error] 1089-1089: Param may be undefined, or defined from star imports

(F405)

🤖 Prompt for AI Agents 
In `@src/cpu/pred/BranchPredictor.py` around lines 1063 - 1089, The MicroTAGE
Python config declares parameters not used by its C++ constructor; remove the
unused Param entries baseTableSize, enableSC, useAltOnNaSize, and
useAltOnNaWidth from the MicroTAGE class so the Python and C++ interfaces match.
Edit the MicroTAGE class (symbols: MicroTAGE, needMoreHistories, updateOnRead,
numPredictors, tableSizes, TTagBitSizes, TTagPcShifts, histLengths, maxHistLen,
numWays, maxBranchPositions, numTablesToAlloc, numBanks, blockSize,
enableBankConflict, numDelay) and delete the four Param.* lines for
baseTableSize, enableSC, useAltOnNaSize, and useAltOnNaWidth leaving only the
actual constructor-backed parameters listed in the review.


class BTBITTAGE(TimedBaseBTBPredictor):
type = 'BTBITTAGE'
Expand Down Expand Up @@ -1169,7 +1186,7 @@ class DecoupledBPUWithBTB(BranchPredictor):
numStages = Param.Unsigned(4, "Maximum number of stages in the pipeline")
ubtb = Param.UBTB(UBTB(), "UBTB predictor")
abtb = Param.AheadBTB(AheadBTB(), "ABTB predictor")
microtage = Param.BTBTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
microtage = Param.MicroTAGE(MicroTAGE(), "MicroTAGE predictor to assist uBTB")
mbtb = Param.MBTB(MBTB(), "MBTB predictor")
tage = Param.BTBTAGE(BTBTAGE(), "TAGE predictor")
ittage = Param.BTBITTAGE(BTBITTAGE(), "ITTAGE predictor")
Expand Down
4 changes: 3 additions & 1 deletion src/cpu/pred/SConscript
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,8 @@ SimObject('BranchPredictor.py', sim_objects=[
'DecoupledStreamBPU', 'DefaultFTB', 'DecoupledBPUWithFTB',
'TimedBaseFTBPredictor', 'FTBTAGE', 'FTBRAS', 'FTBuRAS', 'FTBITTAGE',
'AheadBTB', 'MBTB', 'UBTB', 'DecoupledBPUWithBTB',
'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])
'TimedBaseBTBPredictor', 'BTBRAS', 'BTBTAGE', 'MicroTAGE',
'BTBITTAGE', 'BTBMGSC'], enums=["BpType"])

DebugFlag('Indirect')
Source('bpred_unit.cc')
Expand Down Expand Up @@ -100,6 +101,7 @@ Source('btb/abtb.cc')
Source('btb/mbtb.cc')
Source('btb/timed_base_pred.cc')
Source('btb/btb_tage.cc')
Source('btb/microtage.cc')
Source('btb/btb_ittage.cc')
Source('btb/btb_mgsc.cc')
Source('btb/folded_hist.cc')
Expand Down
1 change: 1 addition & 0 deletions src/cpu/pred/btb/decoupled_bpred.cc
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Expand Up @@ -133,6 +133,7 @@ DecoupledBPUWithBTB::tick()
tage->dryRunCycle(s0PC);
DPRINTF(Override, "Squashing, BPU state updated.\n");
squashing = false;
//here need
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⚠️ Potential issue | 🟡 Minor

Clarify or remove the incomplete comment.

Line 136’s //here need reads like a half‑finished TODO; please replace it with an actionable note or remove it.

🧹 Suggested cleanup 
-        //here need
📝 Committable suggestion

‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.

Suggested change
//here need
🤖 Prompt for AI Agents 
In `@src/cpu/pred/btb/decoupled_bpred.cc` at line 136, Replace the incomplete
comment "//here need" with either a clear, actionable comment explaining what's
required at that spot (e.g., why a particular operation is necessary, what
invariant must hold, or what TODO remains with expected behavior and a
JIRA/issue ID) or simply remove it if no note is needed; locate the comment near
the decoupled branch predictor logic in decoupled_bpred.cc (around the relevant
function handling branch prediction) and ensure the new comment references the
specific reason or next step so future readers understand intent.

return;
}

Expand Down
6 changes: 4 additions & 2 deletions src/cpu/pred/btb/decoupled_bpred.hh
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Expand Up @@ -16,14 +16,16 @@
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/pred/bpred_unit.hh"
#include "cpu/pred/btb/abtb.hh"
#include "cpu/pred/btb/mbtb.hh"
#include "cpu/pred/btb/btb_ittage.hh"
#include "cpu/pred/btb/btb_mgsc.hh"
#include "cpu/pred/btb/btb_tage.hh"
#include "cpu/pred/btb/btb_ubtb.hh"
#include "cpu/pred/btb/btb_mgsc.hh"
#include "cpu/pred/btb/jump_ahead_predictor.hh"
#include "cpu/pred/btb/loop_buffer.hh"
#include "cpu/pred/btb/loop_predictor.hh"
#include "cpu/pred/btb/mbtb.hh"
#include "cpu/pred/btb/microtage.hh"
#include "cpu/pred/btb/ras.hh"
#include "cpu/pred/general_arch_db.hh"

Expand Down Expand Up @@ -94,7 +96,7 @@ class DecoupledBPUWithBTB : public BPredUnit
UBTB *ubtb{};
AheadBTB *abtb{};
MBTB *mbtb{};
BTBTAGE *microtage{};
MicroTAGE *microtage{};
BTBTAGE *tage{};
BTBITTAGE *ittage{};
BTBMGSC *mgsc{};
Expand Down
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