cpu

• homemade
• turing complete 16-bit Von Neumann-like CISC CPU made in Logisim Evolution (v3.9.0)
• single-cycle
• 1 rom for program code and 2 roms for microcode (FSM and decoding)
• 2 main buses -> data bus and address bus
• 1 16-bit register file holding 7 general purpose registers and SP
• 16-bit addressable ram (internal memory)
• word size -> 16 bits
• 3 t-stages micro-sequencer (fetch -> decode -> execute; one t-stage for each FSM stage) for one-shot instructions
• +4 t-stages for multi-shot instructions
• 64 possible instructions

v1 - turing complete version

• non microcoded decoder
• ISA16
• FSM microcode

v2 - current version

• FSM microcode
• microcode

ISA

opcode	operand 1	flag/IMM_EXT	immediate/operand 2
bits 15:10	bits 9:7	bit 6	bits 5:0/bits 2:0

• fixed instruction width
• little endian

vector	mnemonic	opcode
DCD - O0		0x0000 (NULL)
DCD - O1	hlt	0x0400
DCD - O2	ld reg (op), [addr (imm)]	0x0a00 (r0 IMM_EXT); 0x08**, 0x088*, 0x09**, 0x098*, 0x0A**, 0x0A8*, 0x0B**, 0x0B8* (r0–r7 ¬IMM-EXT)
DCD - O3	out [addr]	0x0E00 (IMM_EXT); 0x0C** (¬IMM_EXT)
DCD - O4	st reg (op), [addr (imm)]	0x1200 (r0 IMM_EXT); 0x10** (r0 ¬IMM_EXT)
DCD - O5	ld reg (op), val (imm)	0x1600 (r0 IMM_EXT); 0x14**, 0x148* (r0-r1 ¬IMM_EXT)
DCD - O6	jmp addr	0x1a00 (r0 IMM_EXT); 0x18** (r0 ¬IMM_EXT);
DCD - O7	add reg, reg	0x1C** (ex: 0x1C01)
DCD - O8	sub reg, reg	0x20** (ex: 0x2001)
DCD - O9	mul reg, reg	0x24** (ex: 0x2401)
DCD - O10	div reg, reg	0x28** (ex: 0x2801)
DCD - O11	rem reg, reg	0x2C** (ex: 0x2C01)
DCD - O12	cmp reg, reg	0x30** (ex: 0x3001)
DCD - O13	jz addr	0x3600 (IMM_EXT); 0x34** (¬IMM_EX)
DCD - O14	st reg (op), [addr (reg-imm)]	0x38**
DCD - O15	ld reg (op), [addr (reg-imm)]	0x3C**
DCD - O16	ld reg (op), reg (imm)	0x40**

1. O0 -> WIP #UD
   • T2-a: (resistor / reserved)
2. O1 -> hlt
   • T2-a: HALT
3. O2 -> ld reg1, [addr]
   • reg1 -> opr (destination)
   • addr -> imm (source)
   • T2-a: MAR <- (PC++)WORD
   • T2-b: RAM[MAR] -> RF[reg1]
   • t (T2-a) -> OP_COUNTER_ENB, OP_ROM_OUT, CROSS_BUS1, OP_MAR_IN
   • t + 1 (T2-b) -> MAR_OUT, RAM_OUT, OPR_OUT, RF_IN, EOI
4. O3 -> out [addr]
   • addr -> imm (destination)
   • T2-a: MAR <- (PC++)WORD
   • T2-b: RAM[MAR] -> OTR
   • t (T2-a) -> OP_COUNTER_ENB, OP_ROM_OUT, CROSS_BUS1, OP_MAR_IN
   • t + 1 (T2-b) -> MAR_OUT, RAM_OUT, OUTPUT_REG_IN, EOI
5. O4 -> st reg1, [addr]
   • reg1 -> opr (source)
   • addr -> imm (destination)
   • T2-a: MAR <- (PC++)WORD
   • T2-b: RF[reg1] -> RAM[MAR]
   • t (T2-a) -> OP_COUNTER_ENB, OP_ROM_OUT, CROSS_BUS1, OP_MAR_IN
   • t + 1 (T2-b) -> OPR_OUT, RF_A_OUT, MAR_OUT, RAM_IN, EOI
6. O5 -> ld reg1, val
   • val -> imm (source)
   • reg1 -> opr (destination)
   • T2-a -> IMR <- (PC++)WORD
   • T2-b -> IMR -> RF[reg1]
   • t (T2-a) -> OP_COUNTER_ENB, OP_ROM_OUT, OP_IMR_IN
   • t + 1 (T2-b) -> IMR_OUT, OPR_OUT, RF_IN, EOI
7. O6 -> jmp addr
   • addr -> imm (destination)
   • T2-a -> MAR <- (PC++)WORD
   • T2-b -> JMP[MAR]
   • t (T2-a) -> OP_COUNTER_ENB, OP_ROM_OUT, CROSS_BUS1, OP_MAR_IN
   • t + 1 (T2-b) -> MAR_OUT, JUMP, EOI
8. O7 -> add reg1, reg2
   • reg1 -> opr (destination)
   • reg2 -> imm (source)
   • T2-a -> reg1 <- ALU(ADD(reg 1, reg2))
   • t (T2-a) -> ALU_OPS, RF_A_ALU_OUT, RF_B_ENB, RF_B_ALU_OUT, IMR_RF_OUT, OPR_OUT, ALU_OUT, RF_IN, EOI
9. O8 -> sub reg1, reg2
   • reg1 -> opr (destination)
   • reg2 -> imm (source)
   • T2-a -> reg1 <- ALU(SUB(reg 1, reg2))
   • t (T2-a) -> ALU_OPS, RF_A_ALU_OUT, RF_B_ENB, RF_B_ALU_OUT, IMR_RF_OUT, OPR_OUT, ALU_OUT, RF_IN, EOI
10. O9 -> mul reg1, reg2
    • reg1 -> opr (destination)
    • reg2 -> imm (source)
    • T2-a -> reg1 <- ALU(MUL(reg 1, reg2))
    • t (T2-a) -> ALU_OPS, RF_A_ALU_OUT, RF_B_ENB, RF_B_ALU_OUT, IMR_RF_OUT, OPR_OUT, ALU_OUT, RF_IN, EOI
11. O10 -> div reg1, reg2
    • reg1 -> opr (destination)
    • reg2 -> imm (source)
    • T2-a -> reg1 <- ALU(DIV(reg 1, reg2))
    • t (T2-a) -> ALU_OPS, RF_A_ALU_OUT, RF_B_ENB, RF_B_ALU_OUT, IMR_RF_OUT, OPR_OUT, ALU_OUT, RF_IN, EOI
12. O11 -> rem reg1, reg2
    • reg1 -> opr (destination)
    • reg2 -> imm (source)
    • T2-a -> reg1 <- ALU(DIV(reg 1, reg2))
    • t (T2-a) -> ALU_OPS, REM_ENB, RF_A_ALU_OUT, RF_B_ENB, RF_B_ALU_OUT, IMR_RF_OUT, OPR_OUT, ALU_OUT, RF_IN, EOI
13. O12 -> cmp reg, reg
    • reg1 -> opr
    • reg2 -> imm
    • T2-a -> reg1 <- ALU(SUB(reg 1, reg2))
    • t (T2-a) -> ALU_OPS, RF_A_ALU_OUT, RF_B_ENB, RF_B_ALU_OUT, IMR_RF_OUT, OPR_OUT, FLAGS_IN, EOI
14. O13 -> jz addr
    • addr -> imm (destination)
    • T2-a -> MAR <- (PC++)WORD
    • T2-b -> JMP[MAR]
    • t (T2-a) -> OP_COUNTER_ENB, OP_ROM_OUT, CROSS_BUS1, OP_MAR_IN
    • t + 1 (T2-b) -> MAR_OUT, JZ, EOI
15. O14 -> st reg1, [reg2]
    • reg1 -> opr (source)
    • reg2 -> imm (destination)
    • T2-a: MAR <- RF[reg2]
    • T2-b: RF[reg1] -> RAM[MAR]
    • t (T2-a) -> OP_MAR_IN, RF_B_ENB, RF_B_OUT, CROSS_BUS ->
    • t + 1 (T2-b) -> OPR_OUT, RF_A_OUT, MAR_OUT, RAM_IN, EOI
16. O15 -> ld reg1, [reg2]
    • reg1 -> opr (destination)
    • reg2 -> imm (source)
    • T2-a: MAR <- RF[reg2]
    • T2-b: RF[reg1] <- RAM[MAR]
    • t (T2-a) -> OP_MAR_IN, RF_B_ENB, RF_B_OUT, CROSS_BUS ->
    • t + 1 (T2-b) -> MAR_OUT, RAM_OUT, OPR_OUT, RF_A_IN, EOI
17. O16 -> ld reg1, reg2
    • reg1 -> opr (destination)
    • reg2 -> imm (source)
    • T2-a: RF[reg1] <- RF[reg2]
    • t (T2-a) -> RF_INTERNAL_OP, IMR_RF_OUT, B_ENB, B_OUT, OPR_OUT, RF_IN, EOI

control signals distribution

bit 27: CROSS_BUS2
bit 26: OP_COUNTER_ENB
bit 25: OP_ROM_OUT
bit 24: OP_IMR_IN
bit 23: RF_B_OUT
bit 22: OP_MAR_IN
bit 21: REM_ENB
bit 20: RF_A_ALU_OUT
bit 19: RF_B_ALU_OUT
bit 18: RF_B_ENB
bit 17: CROSS_BUS
bit 16: IMR_RF_OUT
bit 15: JZ
bit 14: RF_INTERNAL_OP
bit 13: ALU_OUT
bit 12: FLAGS_IN
bit 11: JUMP
bit 10: OPR_OUT
bit 9: MAR_OUT
bit 8: RF_A_OUT
bit 7: RAM_IN
bit 6: OUTPUT_REG_IN
bit 5: IMR_OUT
bit 4: RF_IN
bit 3: RAM_OUT
bit 2: HALT
bit 1: NOP
bit 0: EOI

Programs

• Increment to overflow

0x0: ld r0, 1 	; 0x1401
0x1: ld r1, 1 	; 0x1441
0x2: st r1, 0x0 ; 0x1040 
0x3: out 0x0 	; 0x0c00
0x4: add r1, r0 ; 0x1c40
0x5: jmp 0x2 	; 0x1802