fix: default vector int division to signed to match scalar behavior

[Jaskirat-s7]

Fixes the bug reported in the issue regarding inconsistent astx.BinaryOp signedness fallback between scalar and vector operands.

Changes Made:

Updated the vector integer division logic in src/irx/builders/llvmliteir.py to default to unsigned = False (signed division via sdiv) when the unsigned attribute is omitted or set to None.
This unifies the vector fallback logic with the existing scalar fallback behavior and prevents the compiler from throwing an unexpected fatal Exception.
(Tested locally and verified against the existing AST constraint test suite).

[yuvimittal]

@Jaskirat-s7 , could u explain more about the pr please

[Jaskirat-s7]

Hi @yuvimittal,

This PR fixes Issue #204 (Inconsistent integer division signedness fallback between scalar and vector operands).
context:-
Currently, if an astx.BinaryOp node for division (/) does not explicitly define signedness (i.e. unsigned = None), the compiler behaves inconsistently:

• Scalar Division (~L1078): Defaults to signed division and emits an sdiv instruction.
• Vector Division (~L935): Throws a fatal exception ("Cannot infer integer division signedness for vector op") and halts compilation.
  Fix:
  I updated the vector division fallback logic to match the scalar logic. Now, if the unsigned attribute is missing or None on a vector division node, it correctly defaults to unsigned = False and emits a signed sdiv.
  Regarding Testing:
  Please note that I couldn't add a direct AST-level constraint test for this because there are currently no literal vector AST nodes available in astx yet (so the bug can only be triggered by generating the division BinaryOp with known LLVM vectors natively). However, I have verified the fix locally to ensure it successfully prevents the exception and allows compilation to proceed!