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ashs810061/README.md

Hi there 👋

I'm Pin-Hao, a Digital IC / RTL enthusiast from NCHU EE.

⚡ About Me

  • Focus: Verilog/SystemVerilog RTL · AXI4/AXI-Stream/AXI-Lite ·
  • Toolchain: Vivado · ModelSim· Python (Jupyter) · C++/OpenCV · Git/Linux
  • Recent: Built an FPGA-based FAST corner detection prototype.

🧰 Tech Stack

  • RTL: Verilog, SystemVerilog
  • FPGA/SoC: PYNQ-ZU / Zynq MPSoC

📊 GitHub Stats

Top Langs

⭐ Featured Project

FAST Corner Detection Accelerator (FPGA · RTL)
Streaming circle-16 test + NMS, II=1 @ 100 MHz, ORBextractor-friendly output.
➡ Repo: https://github.com/ashs810061/FPGA-FAST-Corner-Detector

📫 Contact

Popular repositories Loading

  1. Design-and-Implementation-of-an-Energy-Efficient-FAST-Corner-Detection-Accelerator-on-PYNQ Design-and-Implementation-of-an-Energy-Efficient-FAST-Corner-Detection-Accelerator-on-PYNQ Public

    High-performance FAST Corner Detector on PYNQ with using Hardware Acceleration (80+ FPS).

    Verilog 1

  2. ashs810061 ashs810061 Public