Round-trip testing POC

monitor/src/interpreter.rs

@@ -50,28 +50,15 @@ impl Interpreter {
         &self,
         struct_name: Option<String>,
         ctx: &GlobalContext,
-        trace: &WaveSignalTrace,
+        _trace: &WaveSignalTrace,
     ) -> ProtocolApplication {
         let mut serialized_args = vec![];
         for arg in &self.transaction.args {
             let symbol_id = arg.symbol();
-            let name = self.symbol_table[symbol_id].full_name(&self.symbol_table);
-            let value = self.args_mapping.get(&symbol_id).unwrap_or_else(|| {
-                let time_str = if ctx.show_waveform_time {
-                    trace.format_time(trace.time_step(), ctx.time_unit)
-                } else {
-                    format!("cycle {}", self.trace_cycle_count)
-                };
-                panic!(
-                    "Transaction `{}`, {}: Unable to find value for {} ({}) in args_mapping, which is {{ {} }}",
-                    self.transaction.name,
-                    time_str,
-                    name,
-                    symbol_id,
-                    serialize_args_mapping(&self.args_mapping, &self.symbol_table, ctx.display_hex)
-                )
-            });
-            serialized_args.push(serialize_bitvec(value, ctx.display_hex));
+            match self.args_mapping.get(&symbol_id) {
+                Some(value) => serialized_args.push(serialize_bitvec(value, ctx.display_hex)),
+                None => serialized_args.push("?".to_string()),
+            }
         }
         ProtocolApplication {
             struct_name,
@@ -488,7 +475,9 @@ impl Interpreter {
             }
             Stmt::Block(stmt_ids) => {
                 if stmt_ids.is_empty() {
-                    Ok(None)
+                    // Empty block — use next_stmt_map to continue
+                    // to the next statement in the parent scope
+                    Ok(self.next_stmt_map[stmt_id])
                 } else {
                     Ok(Some(stmt_ids[0]))
                 }

monitor/src/scheduler.rs

@@ -430,31 +430,6 @@ impl Scheduler {
                         .collect::<Vec<_>>()
                 )));
             }
-            let finished_thread = &finished[0];
-
-            // ...and there shouldn't be any other threads in `next`
-            let next = threads_with_start_time(&self.next, start_cycle);
-            if !next.is_empty() {
-                let start_time_str = if ctx.show_waveform_time {
-                    trace.format_time(finished_thread.start_time_step, ctx.time_unit)
-                } else {
-                    format!("cycle {}", finished_thread.start_cycle)
-                };
-                let error_context = anyhow!(
-                    "Thread {} (`{}`) finished but there are other threads with the same start time ({}) in the `next` queue, namely {:?}",
-                    finished_thread.global_thread_id(ctx),
-                    finished_thread.transaction.name,
-                    start_time_str,
-                    next.iter()
-                        .map(|t| t.transaction.name.clone())
-                        .collect::<Vec<_>>()
-                );
-
-                return Err(SchedulerError::NoTransactionsMatch {
-                    struct_name: self.struct_name.clone(),
-                    error_context,
-                });
-            }
         }
 
         // Next, find the unique start cycles of all threads in `failed`
@@ -748,6 +723,18 @@ impl Scheduler {
                     }
                 }
                 Ok(None) => {
+                    // Check if the last executed statement was `step()`.
+                    // If not, this protocol is ill-formed and should be discarded.
+                    if !matches!(thread.transaction[current_stmt_id], Stmt::Step) {
+                        info!(
+                            "Thread {} (`{}`) didn't end with `step()`, marking as failed.",
+                            thread.global_thread_id(ctx),
+                            self.format_transaction_name(ctx, thread.transaction.name.clone())
+                        );
+                        self.failed.push_back(thread);
+                        return Ok(ThreadResult::Completed);
+                    }
+
                     // Check if another thread has already finished in this cycle.
                     // Invariant: Only one thread per struct can finish per cycle
                     if let Some((first_start_cycle, first_thread_id, first_transaction_name)) =

monitor/tests/fpga-debugging/axi-stream-s2/s2_buggy.out

@@ -14,25 +14,4 @@ trace {
     recv(4);  // [time: 937.5ns -> 962.5ns]
     recv(5);  // [time: 962.5ns -> 987.5ns]
     recv(6);  // [time: 987.5ns -> 1012.5ns]
-    stall(7, 0);  // [time: 1012.5ns -> 1037.5ns]
-    stall(7, 1);  // [time: 1037.5ns -> 1050ns]
-}
-
-// trace 1
-trace {
-    reset();  // [time: 0ns -> 12.5ns]
-    wait_for_data();  // [time: 337.5ns -> 362.5ns]
-    wait_for_data();  // [time: 387.5ns -> 412.5ns]
-    wait_for_data();  // [time: 512.5ns -> 537.5ns]
-    wait_for_data();  // [time: 537.5ns -> 562.5ns]
-    wait_for_data();  // [time: 612.5ns -> 637.5ns]
-    wait_for_data();  // [time: 787.5ns -> 812.5ns]
-    wait_for_data();  // [time: 837.5ns -> 862.5ns]
-    recv(1);  // [time: 862.5ns -> 887.5ns]
-    recv(2);  // [time: 887.5ns -> 912.5ns]
-    recv(3);  // [time: 912.5ns -> 937.5ns]
-    recv(4);  // [time: 937.5ns -> 962.5ns]
-    recv(5);  // [time: 962.5ns -> 987.5ns]
-    recv(6);  // [time: 987.5ns -> 1012.5ns]
-    stall(7, 1);  // [time: 1037.5ns -> 1050ns]
 }

monitor/tests/fpga-debugging/axi-stream-s2/s2_fixed.out

@@ -14,34 +14,12 @@ trace {
     recv(4);  // [time: 937.5ns -> 962.5ns]
     recv(5);  // [time: 962.5ns -> 987.5ns]
     recv(6);  // [time: 987.5ns -> 1012.5ns]
-    stall(7, 0);  // [time: 1012.5ns -> 1037.5ns]
-    stall(7, 0);  // [time: 1037.5ns -> 1062.5ns]
+    stall(7, 0);  // [time: 1012.5ns -> 1062.5ns]
     reset();  // [time: 1062.5ns -> 1087.5ns]
     reset();  // [time: 1087.5ns -> 1100ns]
 }
 
 // trace 1
-trace {
-    reset();  // [time: 0ns -> 12.5ns]
-    wait_for_data();  // [time: 337.5ns -> 362.5ns]
-    wait_for_data();  // [time: 387.5ns -> 412.5ns]
-    wait_for_data();  // [time: 512.5ns -> 537.5ns]
-    wait_for_data();  // [time: 537.5ns -> 562.5ns]
-    wait_for_data();  // [time: 612.5ns -> 637.5ns]
-    wait_for_data();  // [time: 787.5ns -> 812.5ns]
-    wait_for_data();  // [time: 837.5ns -> 862.5ns]
-    recv(1);  // [time: 862.5ns -> 887.5ns]
-    recv(2);  // [time: 887.5ns -> 912.5ns]
-    recv(3);  // [time: 912.5ns -> 937.5ns]
-    recv(4);  // [time: 937.5ns -> 962.5ns]
-    recv(5);  // [time: 962.5ns -> 987.5ns]
-    recv(6);  // [time: 987.5ns -> 1012.5ns]
-    stall(7, 0);  // [time: 1012.5ns -> 1037.5ns]
-    reset();  // [time: 1062.5ns -> 1087.5ns]
-    reset();  // [time: 1087.5ns -> 1100ns]
-}
-
-// trace 2
 trace {
     reset();  // [time: 0ns -> 12.5ns]
     wait_for_data();  // [time: 337.5ns -> 362.5ns]

monitor/tests/fpga-debugging/axi-stream-s2/s2_fixed.prot

@@ -90,6 +90,8 @@ prot stall<DUT: AXISManager>(out data: u32, out last: u1) {
     // Verify outputs remained stable during the stall
     assert_eq(DUT.i_tdata, data);
     assert_eq(DUT.i_tlast, last);
+    fork();
+    step();
 }
 
 // WAIT_FOR_DATA: Receiver is ready but no data is available

protocols/src/scheduler.rs

@@ -403,6 +403,10 @@ impl<'a> Scheduler<'a> {
             }
         }
 
+        // Final sim step so the FST waveform always has at least one time entry
+        // (needed for combinational-only designs where no cycle advances occur)
+        self.evaluator.sim_step();
+
         // Emit diagnostics for all errors after execution is complete
         self.emit_all_diagnostics();
         self.results.clone()

scripts/roundtrip.out

@@ -0,0 +1,32 @@
+
+=== Round-trip results ===
+  Passed:  28 / 33
+  Failed:  5 / 33
+  Skipped: 38 (transactions don't complete successfully)
+
+Monitor failures:
+
+  --- protocols/tests/adders/adder_d1/busy_wait_pass.tx (trace 0) ---
+  thread 'main' panicked at monitor/src/interpreter.rs:466:17:
+  not yet implemented: Bounded loops is not yet implemented in the monitor
+  note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
+
+  --- protocols/tests/adders/adder_d1/loop_with_assigns.tx (trace 0) ---
+  thread 'main' panicked at monitor/src/interpreter.rs:466:17:
+  not yet implemented: Bounded loops is not yet implemented in the monitor
+  note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
+
+  --- protocols/tests/adders/adder_d1/nested_busy_wait.tx (trace 0) ---
+  thread 'main' panicked at monitor/src/interpreter.rs:466:17:
+  not yet implemented: Bounded loops is not yet implemented in the monitor
+  note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
+
+  --- protocols/tests/fifo/push_pop_loop_empty.tx (trace 0) ---
+  thread 'main' panicked at monitor/src/interpreter.rs:466:17:
+  not yet implemented: Bounded loops is not yet implemented in the monitor
+  note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace
+
+  --- protocols/tests/fifo/push_pop_loop_not_empty.tx (trace 0) ---
+  thread 'main' panicked at monitor/src/interpreter.rs:466:17:
+  not yet implemented: Bounded loops is not yet implemented in the monitor
+  note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace