(WIP) [Interp] Port axi-stream-s2 BNW bug for interpreter, rewrite using repeat loops#188
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(WIP) [Interp] Port axi-stream-s2 BNW bug for interpreter, rewrite using repeat loops#188
axi-stream-s2 BNW bug for interpreter, rewrite using repeat loops#188Conversation
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TODOs:
.protfiles for the monitor + interpreter (i.e. update the monitor version to refer to the pins in the internal Verilog file instead of the external wrapper module)#[idle]pragma (always printidle()transactions) #189s2_buggy.prot/s2_fixed.protthat usesrepeatloops