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Simple 3-stage pipeline RISC-V processor
C 143 33
Generate BTF trace file for FreeRTOS
C 4 2
Generating the call graph from elf binary file
Assembly 39 1
A basic component for pipelined control
SystemVerilog 1
An example to test srv32 RISC-V core on FreeRTOS
Makefile 8 3
C
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