Tried running on Verilator

.gitignore

@@ -6,3 +6,6 @@
 /*.vid
 /*.mkv
 /DMG_ROM.bin
+obj_dir
+obj-gameboy
+obj-debug

Makefile

@@ -181,7 +181,7 @@ mkvid/mkimgs: mkvid/mkimgs.c
 boot/quickboot.bin:
 	make -C boot
 
-.PHONY: test test-all test-cpu test-boot
+.PHONY: test test-all test-cpu test-boot verilator verilator-test
 
 TEST_DEPENDENCIES = dmg_cpu_b_gameboy.vvp boot/quickboot.bin mkvid/mkimgs
 
@@ -197,3 +197,56 @@ test-cpu: $(TEST_DEPENDENCIES)
 test-boot: $(TEST_DEPENDENCIES)
 	tests/run_tests.sh boot
 
+verilator:
+	verilator --Mdir obj-gameboy \
+		-Wno-fatal --timing  --cc --trace-fst \
+		--top-module dmg_cpu_b_gameboy \
+		--binary -j 0 \
+		$(AV_DUMP) dmg_cpu_b_gameboy.sv $(DMG_CPU_B) $(SM83) $(MBC)
+
+# same as above, but without trace
+verilator-test:
+	verilator --Mdir obj-test \
+		--debug \
+		-Wno-fatal --timing  --cc \
+		--top-module dmg_cpu_b_gameboy \
+		--binary -j 0 \
+		$(AV_DUMP) dmg_cpu_b_gameboy.sv $(DMG_CPU_B) $(SM83) $(MBC)
+
+verilator-debug:
+	verilator --Mdir obj-debug \
+		-CFLAGS -DVL_DEBUG=1 \
+		--debug --trace-fst \
+		-Wno-fatal --timing  --cc \
+		--top-module dmg_cpu_b_gameboy \
+		--binary -j 0 \
+		$(AV_DUMP) dmg_cpu_b_gameboy.sv $(DMG_CPU_B) $(SM83) $(MBC)
+
+sim-verilator: verilator
+	./obj-gameboy/Vdmg_cpu_b_gameboy +DUMPFILE=dmg_cpu_b_gameboy_ver.fst \
+	                       $(call VVP_CH_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                       $(call VVP_SND_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                       $(call VVP_VID_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                       +BOOTROM="$(BOOTROM)" \
+	                       +ROM="$(ROM)" \
+	                       +SECS=$(SECS)
+
+sim-verilator-test: verilator-test
+	./obj-test/Vdmg_cpu_b_gameboy \
+	                       $(call VVP_CH_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                       $(call VVP_SND_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                       $(call VVP_VID_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                       +BOOTROM="$(BOOTROM)" \
+	                       +ROM="$(ROM)" \
+	                       +SECS=$(SECS)
+
+sim-verilator-debug: verilator-debug
+	./obj-debug/Vdmg_cpu_b_gameboy \
+	                    	$(call VVP_CH_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                    	$(call VVP_SND_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                    	$(call VVP_VID_DUMP_FLAGS,dmg_cpu_b_gameboy) \
+	                    	+verilator+debug \
+	                    	+BOOTROM="$(BOOTROM)" \
+	                    	+ROM="$(ROM)" \
+	                    	+SECS=$(SECS)
+

dmg_cpu_b/cells/dffr_a.sv

@@ -23,6 +23,6 @@ module dffr_a #(
 			ff <= 0;
 	end
 
-	assign #T_DFFR_A q = ff;
+	assign q = ff;
 
 endmodule

dmg_cpu_b/cells/dffr_b.sv

@@ -20,6 +20,6 @@ module dffr_b #(
 			ff <= 0;
 	end
 
-	assign #T_DFFR_B q = ff;
+	assign q = ff;
 
 endmodule

dmg_cpu_b/cells/dffr_bp.sv

@@ -20,6 +20,6 @@ module dffr_bp #(
 			ff <= 0;
 	end
 
-	assign #T_DFFR_BP q = ff;
+	assign q = ff;
 
 endmodule

dmg_cpu_b/cells/dffsr.sv

@@ -40,6 +40,6 @@ module dffsr #(
 			nreset_posedge <= 0;
 	end
 
-	assign #T_DFFSR q = ff;
+	assign q = ff;
 
 endmodule

dmg_cpu_b/cells/dlatch_a.sv

@@ -16,6 +16,6 @@ module dlatch_a #(
 			l = d;
 	end
 
-	assign #T_DL_A q = l;
+	assign q = l;
 
 endmodule

dmg_cpu_b/cells/dlatch_b.sv

@@ -14,6 +14,6 @@ module dlatch_b(
 			l = d;
 	end
 
-	assign #T_DL_B q = l;
+	assign q = l;
 
 endmodule

dmg_cpu_b/cells/drlatch.sv

@@ -18,6 +18,6 @@ module drlatch #(
 			l = d;
 	end
 
-	assign #T_DRL q = l;
+	assign q = l;
 
 endmodule

dmg_cpu_b/cells/nand_srlatch.sv

@@ -25,7 +25,7 @@ module nand_srlatch(
 		end
 	end
 
-	assign #T_SRL q  = lp;
-	assign #T_SRL nq = lm;
+	assign q  = lp;
+	assign nq = lm;
 
 endmodule

dmg_cpu_b/cells/nor_srlatch.sv

@@ -25,7 +25,7 @@ module nor_srlatch(
 		end
 	end
 
-	assign #T_SRL q  = lp;
-	assign #T_SRL nq = lm;
+	assign q  = lp;
+	assign nq = lm;
 
 endmodule

dmg_cpu_b/cells/tffd.sv

@@ -27,6 +27,6 @@ module tffd #(
 			load_negedge <= 0;
 	end
 
-	assign #T_TFFD q = load ? d : ff;
+	assign q = load ? d : ff;
 
 endmodule

dmg_cpu_b/dmg_cpu_b.sv

@@ -114,15 +114,15 @@ module dmg_cpu_b(
 		for (genvar i = 0; i < 8; i++)
 			assign d_pin_drv[i] = bidir_out(d_d[i], d_a[i]);
 	endgenerate
-	assign (pull1, highz0) d_pin = {8{!lula}};
+	assign (pull1, weak0) d_pin = {8{!lula}};
 	assign                 d_pin = d_pin_drv;
 
 	logic [7:0] md_pin_drv; /* Value driven internally onto the pins if not 'z */
 	generate
 		for (genvar i = 0; i < 8; i++)
 			assign md_pin_drv[i] = bidir_out(md_out[i], md_a[i]);
 	endgenerate
-	assign (pull1, highz0) md_pin = {8{!md_b}};
+	assign (pull1, weak0) md_pin = {8{!md_b}};
 	assign                 md_pin = md_pin_drv;
 
 	generate
@@ -135,19 +135,19 @@ module dmg_cpu_b(
 	assign                 sout = nsout;
 	assign                 sin  = bidir_out(sin_d, sin_a);
 	assign                 sck  = bidir_out(sck_d, sck_a);
-	assign (pull1, highz0) sin  = !sin_b;
-	assign (pull1, highz0) sck  = !sck_dir;
+	assign (pull1, weak0) sin  = !sin_b;
+	assign (pull1, weak0) sck  = !sck_dir;
 
 	assign                 p10  = bidir_out(p10_d, p10_a);
 	assign                 p11  = bidir_out(p11_d, p11_a);
 	assign                 p12  = bidir_out(p12_d, p12_a);
 	assign                 p13  = bidir_out(p13_d, p13_a);
 	assign                 p14  = bidir_out(p14_b, p14_a);
 	assign                 p15  = bidir_out(p15_b, p15_a);
-	assign (pull1, highz0) p10  = !p10_b;
-	assign (pull1, highz0) p11  = !p11_b;
-	assign (pull1, highz0) p12  = !p12_b;
-	assign (pull1, highz0) p13  = !p13_b;
+	assign (pull1, weak0) p10  = !p10_b;
+	assign (pull1, weak0) p11  = !p11_b;
+	assign (pull1, weak0) p12  = !p12_b;
+	assign (pull1, weak0) p13  = !p13_b;
 
 	assign cpg = !npin_cpg;
 	assign cp  = !ncp;
@@ -433,6 +433,8 @@ module dmg_cpu_b(
 		string bootrom_file;
 		int f, _;
 
+		$display("DMG CPU B: Starting up...");
+
 		bootrom_file = "";
 		_ = $value$plusargs("BOOTROM=%s", bootrom_file);
 

dmg_cpu_b/pages/p10_apu_decode.sv

@@ -16,33 +16,33 @@ module apu_decode(
 	);
 
 	logic amus, byko, akug, atoz, acat;
-	assign #T_NOR  amus = !(a[7] || a[4] || a[3] || a[2] || a[1] || a[0]);
-	assign #T_AND  anap = amus && ffxx;
-	assign #T_INV  byko = !a[5];
-	assign #T_INV  akug = !a[6];
-	assign #T_NAND atoz = !(byko && akug && cpu_wr && anap);
-	assign #T_AND  acat = anap && cpu_rd && akug && byko;
+	assign  amus = !(a[7] || a[4] || a[3] || a[2] || a[1] || a[0]);
+	assign  anap = amus && ffxx;
+	assign  byko = !a[5];
+	assign  akug = !a[6];
+	assign atoz = !(byko && akug && cpu_wr && anap);
+	assign  acat = anap && cpu_rd && akug && byko;
 	assign ff00wr = atoz;
 	assign ff00rd = acat;
 
 	logic boxy, awet, bezy, avun, asad, acom, baro, atup, ateg, buno, banu, cona, doxy, bafu, bogy, tace, nff1x;
 	logic ff2x, nff2x;
-	assign #T_INV  boxy = !a[5];
-	assign #T_OR   awet = a[4] || boxy || a[6] || a[7];
-	assign #T_OR   bezy = awet || nffxx;
-	assign #T_INV  avun = !a[7];
-	assign #T_INV  asad = !a[6];
-	assign #T_NAND acom = !(avun && asad && a[5] && a[4]);
-	assign #T_NOR  baro = !(acom || nffxx);
-	assign #T_INV  atup = !a[4];
-	assign #T_OR   ateg = atup || a[5] || a[6] || a[7];
-	assign #T_NOR  buno = !(nffxx || ateg);
-	assign #T_INV  banu = !buno;
-	assign #T_INV  cona = !nff2x;
-	assign #T_AND  doxy = cona && xxx6;
-	assign #T_INV  bafu = !cpu_wr;
-	assign #T_INV  bogy = !bafu;
-	assign #T_AND  tace = nch1_amp_en && nch2_amp_en && nff1a_d7 && nch4_amp_en;
+	assign  boxy = !a[5];
+	assign   awet = a[4] || boxy || a[6] || a[7];
+	assign   bezy = awet || nffxx;
+	assign  avun = !a[7];
+	assign  asad = !a[6];
+	assign acom = !(avun && asad && a[5] && a[4]);
+	assign  baro = !(acom || nffxx);
+	assign  atup = !a[4];
+	assign   ateg = atup || a[5] || a[6] || a[7];
+	assign  buno = !(nffxx || ateg);
+	assign  banu = !buno;
+	assign  cona = !nff2x;
+	assign  doxy = cona && xxx6;
+	assign  bafu = !cpu_wr;
+	assign  bogy = !bafu;
+	assign  tace = nch1_amp_en && nch2_amp_en && nff1a_d7 && nch4_amp_en;
 	assign nff2x   = bezy;
 	assign ff3x    = baro;
 	assign nff1x   = banu;
@@ -55,55 +55,55 @@ module apu_decode(
 	logic dupo, datu, daza, dura, duvu, dofa, damy, dufe, duno, dewa, dejy, dona, dafy, emos;
 	logic ekag, esot, egen, exat, emax, etuf, gany, dyva, cafy, covy, cora, dutu, ekez, edaf;
 	logic cuge, caxe, covo, doza, danu, dara, feny, duja, dugo, emor, dusa, deco, gefo, xxx6;
-	assign #T_INV  dyte = !a[0];
-	assign #T_INV  doso = !dyte;
-	assign #T_INV  afob = !a[1];
-	assign #T_INV  dupa = !afob;
-	assign #T_INV  abub = !a[2];
-	assign #T_INV  deno = !abub;
-	assign #T_INV  acol = !a[3];
-	assign #T_INV  duce = !acol;
-	assign #T_NAND dupo = !(acol && abub && afob && dyte);
-	assign #T_NAND datu = !(dyte && afob && deno && acol);
-	assign #T_NAND daza = !(acol && deno && dupa && dyte);
-	assign #T_NAND dura = !(doso && afob && deno && acol);
-	assign #T_NAND duvu = !(acol && deno && dupa && doso);
-	assign #T_AND  dofa = acol && abub && dupa && dyte;
-	assign #T_NAND damy = !(acol && abub && dupa && dyte);
-	assign #T_NAND dufe = !(doso && dupa && abub && acol);
-	assign #T_NAND duno = !(acol && abub && afob && doso);
-	assign #T_NAND dewa = !(doso && afob && abub && acol);
-	assign #T_NAND dejy = !(duce && abub && afob && doso);
-	assign #T_NAND dona = !(dyte && afob && abub && acol);
-	assign #T_NAND dafy = !(duce && abub && afob && dyte);
-	assign #T_NAND emos = !(doso && afob && deno && duce);
-	assign #T_AND  ekag = acol && deno && dupa && dyte;
-	assign #T_NAND esot = !(acol && deno && afob && dyte);
-	assign #T_NAND egen = !(dyte && dupa && deno && duce);
-	assign #T_NAND exat = !(duce && abub && dupa && dyte);
-	assign #T_NAND emax = !(doso && dupa && abub && duce);
-	assign #T_NAND etuf = !(acol && abub && dupa && doso);
-	assign #T_NAND gany = !(duce && deno && afob && dyte);
-	assign #T_NOR  dyva = !(dupo || nff1x);
-	assign #T_NOR  cafy = !(datu || nff2x);
-	assign #T_NOR  covy = !(daza || nff1x);
-	assign #T_NOR  cora = !(dura || nff2x);
-	assign #T_NOR  dutu = !(duvu || nff1x);
-	assign #T_AND  ekez = dofa && ff2x;
-	assign #T_NOR  edaf = !(damy || nff1x);
-	assign #T_NOR  cuge = !(dufe || nff2x);
-	assign #T_NOR  caxe = !(duno || nff1x);
-	assign #T_NOR  covo = !(dewa || nff2x);
-	assign #T_NOR  doza = !(dejy || nff1x);
-	assign #T_NOR  danu = !(dona || nff2x);
-	assign #T_NOR  dara = !(dafy || nff1x);
-	assign #T_NOR  feny = !(emos || nff1x);
-	assign #T_NOR  duja = !(esot || nff1x);
-	assign #T_NOR  dugo = !(egen || nff1x);
-	assign #T_NOR  emor = !(exat || nff1x);
-	assign #T_NOR  dusa = !(emax || nff1x);
-	assign #T_NOR  deco = !(etuf || nff1x);
-	assign #T_NOR  gefo = !(gany || nff1x);
+	assign  dyte = !a[0];
+	assign  doso = !dyte;
+	assign  afob = !a[1];
+	assign  dupa = !afob;
+	assign  abub = !a[2];
+	assign  deno = !abub;
+	assign  acol = !a[3];
+	assign  duce = !acol;
+	assign dupo = !(acol && abub && afob && dyte);
+	assign datu = !(dyte && afob && deno && acol);
+	assign daza = !(acol && deno && dupa && dyte);
+	assign dura = !(doso && afob && deno && acol);
+	assign duvu = !(acol && deno && dupa && doso);
+	assign  dofa = acol && abub && dupa && dyte;
+	assign damy = !(acol && abub && dupa && dyte);
+	assign dufe = !(doso && dupa && abub && acol);
+	assign duno = !(acol && abub && afob && doso);
+	assign dewa = !(doso && afob && abub && acol);
+	assign dejy = !(duce && abub && afob && doso);
+	assign dona = !(dyte && afob && abub && acol);
+	assign dafy = !(duce && abub && afob && dyte);
+	assign emos = !(doso && afob && deno && duce);
+	assign  ekag = acol && deno && dupa && dyte;
+	assign esot = !(acol && deno && afob && dyte);
+	assign egen = !(dyte && dupa && deno && duce);
+	assign exat = !(duce && abub && dupa && dyte);
+	assign emax = !(doso && dupa && abub && duce);
+	assign etuf = !(acol && abub && dupa && doso);
+	assign gany = !(duce && deno && afob && dyte);
+	assign  dyva = !(dupo || nff1x);
+	assign  cafy = !(datu || nff2x);
+	assign  covy = !(daza || nff1x);
+	assign  cora = !(dura || nff2x);
+	assign  dutu = !(duvu || nff1x);
+	assign  ekez = dofa && ff2x;
+	assign  edaf = !(damy || nff1x);
+	assign  cuge = !(dufe || nff2x);
+	assign  caxe = !(duno || nff1x);
+	assign  covo = !(dewa || nff2x);
+	assign  doza = !(dejy || nff1x);
+	assign  danu = !(dona || nff2x);
+	assign  dara = !(dafy || nff1x);
+	assign  feny = !(emos || nff1x);
+	assign  duja = !(esot || nff1x);
+	assign  dugo = !(egen || nff1x);
+	assign  emor = !(exat || nff1x);
+	assign  dusa = !(emax || nff1x);
+	assign  deco = !(etuf || nff1x);
+	assign  gefo = !(gany || nff1x);
 	assign xxx6 = ekag;
 	assign ff10 = dyva;
 	assign ff24 = cafy;