This VHDL code implements a counter chip with a maximum value of 63, utilizing a finite state design model. The machine operates through three distinct states.
| State | Description | Action |
|---|---|---|
| init | Triggered by the reset signal | Sets the counter register to zero and the maximum occupancy register to the received signal value. |
| idle | Normal state of the machine | Waits for incoming signals to initiate a change. |
| change | Triggered when X or Y is turned on | Enters a signed adder state, incrementing or decrementing based on the activating signal. Does not activate if both X and Y are on or if count_reg has reached its maximum and X is on. |
| Signal | Description |
|---|---|
| Result | Synchronized with the data stored in the register. |
| X | Increments the count |
| Y | Decrements the count |
| reset | Initialize the machine. |
| Z | Warning Signal |
| max_occupancy | Sets the maximum value for the counter. |