- Georgia Institute of Technology — M.S. Electrical and Computer Engineering (Aug 2024 – Dec 2026), Atlanta, GA
- University of Wisconsin–Madison — B.S. Computer Engineering (Aug 2021 – May 2024), Madison, WI
- Tenstorrent — RISC-V Cores Intern (Jan 2025 – Aug 2025, Austin, TX)
- Brought up the Ascalon single-core design on an emulation platform while optimizing hardware resource utilization.
- Built a custom Linux kernel with OpenSBI and UART polling to accelerate bring-up of embedded workloads.
- Tuned DOOM rendering pipelines in C++ with frame-buffer and memory-efficient data structures for higher FPS on constrained systems.
- Authored C++/SystemVerilog testbenches that validated customer memory subsystems and uncovered pre-silicon bugs.
- Georgia Institute of Technology — Researcher (Sept 2024 – Jan 2025, Atlanta, GA)
- Enhanced GNNBuilder to convert graph neural networks into FPGA implementations that deliver higher inference throughput.
- Profiled and debugged Xilinx Vitis HLS designs to eliminate deadlocks, caching faults, and logic bottlenecks.
- Experimented with pipelining, caching, and out-of-order execution strategies to accelerate state-of-the-art GNN workloads.
- Elvo AI — Software Engineer (Sept 2024 – Jan 2025, San Francisco, CA)
- Architected and delivered an AWS-backed infrastructure stack with secure auth, observability, and autoscaling foundations.
- Delivered the initial Next.js product experience, then rebuilt it as a mobile-first Expo application with shared component libraries.
- Designed ML pipelines and automated agentic workflows that improved operational efficiency by 30%.
- University of Wisconsin–Madison — Undergraduate Student Researcher (Mar 2023 – May 2024, Madison, WI)
- Built a 10 MHz (±25 Hz) digital modulator/demodulator for an IARPA-sponsored communications project.
- Implemented pipelined ASK, BPSK, and MFSK hardware modulation targeting RF antenna systems.
- Hardened FPGA designs for tighter clock stability and delivered higher-fidelity digital PWM control.
- Embedded ML Inference System (May 2024 – Aug 2024) — Designed a custom SystemVerilog RISC-V CPU with ML-specific instructions, integrated camera/peripheral drivers, and achieved a 30% Imagenet inference speedup over a baseline core.
- Tanks! (Jan 2024 – May 2024) — Built an embedded C game targeting a five-stage RISC-V pipeline with interrupts, dynamic branch prediction, and a handcrafted VGA graphics engine. GitHub
- MazeRunner (Aug 2023 – Dec 2023) — Engineered an FPGA-driven robotics platform with custom SystemVerilog I2C/SPI controllers, pipelined PID motor control, and Design Compiler timing closure.
- Languages: SystemVerilog, Embedded C, C/C++, CUDA, Python, Java, Bazel
- Tools: UVM, FreeRTOS, git, gdb, Bash, Cadence Virtuoso, Synopsys ICC, Questa, Quartus, Xilinx Vitis HLS
- Coursework: Generative & Geometric Deep Learning, Computer Architecture, VLSI, Digital System Design & Synthesis, Embedded Systems, Parallel Programming, Operating Systems, Matrix Methods in ML, Artificial Neural Networks
- 📧 rmadith@gmail.com
- 💻 GitHub
- 🚀 Devpost
- 📍 Atlanta, GA