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fix access to vector context #19

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Merged
aap-sc merged 3 commits into from
Jan 29, 2026
Merged

fix access to vector context #19

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db9a4bd
target/riscv: disable cache-on-read for VL and VSTART
aap-sc Jan 26, 2026
1538d76
target/riscv: vstart should be preserved when manipulating vector state
aap-sc Jan 26, 2026
a0dca25
target/riscv: do not cache access to vtype
aap-sc Jan 29, 2026
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27 changes: 16 additions & 11 deletions src/target/riscv/riscv-013.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2320,7 +2320,7 @@ static int try_set_vsew(struct target *target, unsigned int *debug_vsew)

static int prep_for_vector_access(struct target *target,
riscv_reg_t *orig_mstatus, riscv_reg_t *orig_vtype, riscv_reg_t *orig_vl,
unsigned int *debug_vl, unsigned int *debug_vsew)
riscv_reg_t *orig_vstart, unsigned int *debug_vl, unsigned int *debug_vsew)
{
assert(orig_mstatus);
assert(orig_vtype);
Expand All @@ -2337,12 +2337,15 @@ static int prep_for_vector_access(struct target *target,
if (prep_for_register_access(target, orig_mstatus, GDB_REGNO_VL) != ERROR_OK)
return ERROR_FAIL;

/* Save vtype and vl. */
/* Save original vstart, vtype and vl values for later restoration */
if (riscv_reg_get(target, orig_vstart, GDB_REGNO_VSTART) != ERROR_OK)
return ERROR_FAIL;
if (riscv_reg_get(target, orig_vtype, GDB_REGNO_VTYPE) != ERROR_OK)
return ERROR_FAIL;
if (riscv_reg_get(target, orig_vl, GDB_REGNO_VL) != ERROR_OK)
return ERROR_FAIL;

/* Note: vstart may be non-zero at this point. Updating vsew (via VTYPE)
* reset vstart to 0. */
if (try_set_vsew(target, debug_vsew) != ERROR_OK)
return ERROR_FAIL;
/* Set the number of elements to be updated with results from a vector
Expand All @@ -2353,13 +2356,15 @@ static int prep_for_vector_access(struct target *target,
}

static int cleanup_after_vector_access(struct target *target,
riscv_reg_t mstatus, riscv_reg_t vtype, riscv_reg_t vl)
riscv_reg_t mstatus, riscv_reg_t vtype, riscv_reg_t vl, riscv_reg_t vstart)
{
/* Restore vtype and vl. */
/* Restore vtype, vl and vstart. */
if (riscv_reg_write(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
return ERROR_FAIL;
if (riscv_reg_write(target, GDB_REGNO_VL, vl) != ERROR_OK)
return ERROR_FAIL;
if (riscv_reg_write(target, GDB_REGNO_VSTART, vstart) != ERROR_OK)
return ERROR_FAIL;
return cleanup_after_register_access(target, mstatus, GDB_REGNO_VL);
}

Expand All @@ -2371,10 +2376,10 @@ int riscv013_get_register_buf(struct target *target, uint8_t *value,
if (dm013_select_target(target) != ERROR_OK)
return ERROR_FAIL;

riscv_reg_t mstatus, vtype, vl;
riscv_reg_t mstatus, vtype, vl, vstart;
unsigned int debug_vl, debug_vsew;

if (prep_for_vector_access(target, &mstatus, &vtype, &vl,
if (prep_for_vector_access(target, &mstatus, &vtype, &vl, &vstart,
&debug_vl, &debug_vsew) != ERROR_OK)
return ERROR_FAIL;

Expand Down Expand Up @@ -2412,7 +2417,7 @@ int riscv013_get_register_buf(struct target *target, uint8_t *value,
}
}

if (cleanup_after_vector_access(target, mstatus, vtype, vl) != ERROR_OK)
if (cleanup_after_vector_access(target, mstatus, vtype, vl, vstart) != ERROR_OK)
return ERROR_FAIL;

return result;
Expand All @@ -2426,10 +2431,10 @@ int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
if (dm013_select_target(target) != ERROR_OK)
return ERROR_FAIL;

riscv_reg_t mstatus, vtype, vl;
riscv_reg_t mstatus, vtype, vl, vstart;
unsigned int debug_vl, debug_vsew;

if (prep_for_vector_access(target, &mstatus, &vtype, &vl,
if (prep_for_vector_access(target, &mstatus, &vtype, &vl, &vstart,
&debug_vl, &debug_vsew) != ERROR_OK)
return ERROR_FAIL;

Expand All @@ -2451,7 +2456,7 @@ int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
break;
}

if (cleanup_after_vector_access(target, mstatus, vtype, vl) != ERROR_OK)
if (cleanup_after_vector_access(target, mstatus, vtype, vl, vstart) != ERROR_OK)
return ERROR_FAIL;

return result;
Expand Down
10 changes: 5 additions & 5 deletions src/target/riscv/riscv_reg_impl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -195,12 +195,9 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
* CSRs. */
switch (regno) {
case GDB_REGNO_DPC:
case GDB_REGNO_VSTART:
case GDB_REGNO_VXSAT:
case GDB_REGNO_VXRM:
case GDB_REGNO_VLENB:
case GDB_REGNO_VL:
case GDB_REGNO_VTYPE:
case GDB_REGNO_MISA:
case GDB_REGNO_DCSR:
case GDB_REGNO_DSCRATCH0:
Expand All @@ -212,9 +209,12 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
*/
return !is_write;

case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */
case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */
case GDB_REGNO_TDATA2: /* Changes value when tselect is changed. */
case GDB_REGNO_VSTART: /* Changes value when vtype is changed. */
case GDB_REGNO_VL: /* Changes value when vtype is changed. */
case GDB_REGNO_VTYPE: /* Writes to vtype have side effects, so we don't cache it. */
default:
return false;
}
Expand Down