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rtl-design-and-simulation

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ThirupathiReddyPuchakayala / DESIGN-AND-IMPLEMENTATION-OF-CDMA-BASED-LOW-POWER-VLSI-ROUTER

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This project presents a scalable, high-performance VLSI router architecture for Network-on-Chip (NoC) platforms, using Code Division Multiple Access (CDMA) to enable concurrent data transfers with reduced latency and power consumption. Built with Verilog HDL and implemented on an Artix-7 FPGA.

verilog-hdl cdma-communication vlsi-router-design network-on-chip-communication fpga-implementation rtl-design-and-simulation low-power-digital-circuits timing-and-power-analysis concurrent-packet-transmission synthesis-and-testbench-verification
  • Updated Jul 4, 2025
  • Verilog

Manju7882 / 32-bit-ALU-Design-and-Functional-Verification-Verilog

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RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-state output enable. Simulated and verified using Xilinx ISE.

vhdl rtl verilog xilinx vlsi testbench functional-verification arithmatic-operation rtl-design-and-verification rtl-design-and-simulation
  • Updated Jan 3, 2026
  • Verilog

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