refactor: decompose statement generation into modules #261
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Break down the massive `statement.rs` file into logical submodules,
greatly improving code organization and maintainability.
Changes:
- New Directory Structure `llvm_temporary/statement/`:
- `mod.rs`: Main entry point for `generate_statement_ir`.
- `variable.rs`: Variable declaration and initialization (`ASTNode::Variable`).
- `assign.rs`: Assignment (`ASTNode::Assign`).
- `control.rs`: Control flow (`If`, `While`, `Break`, `Continue`, `Return`).
- `io.rs`: Output/Input (`Print`, `Println`, `Input`).
- `asm.rs`: Inline assembly blocks (`AsmBlock`).
- `expr_stmt.rs`: Expression statements (`Expression`).
- Migration:
- Moved logic from the single `generate_statement_ir` function into
specialized functions within each module (e.g., `gen_variable_ir`,
`gen_if_ir`).
- Extracted helper functions like `truthy_to_i1` and `make_global_cstr`
to appropriate modules.
- Functionality:
- Preserved all existing logic.
- No behavioral changes, purely structural refactoring.
This prepares the statement generation logic for future extensions and
makes the codebase easier to navigate.
Signed-off-by: LunaStev <luna@lunastev.org>
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Following the modularization of expression handling, this PR decomposes the massive
statement.rsfile into specialized submodules withinllvm_temporary/src/llvm_temporary/statement/. This structural refactor significantly improves code readability, reduces cognitive load when navigating the backend, and provides a cleaner foundation for future language features.Key Changes
1. Module Reorganization
The monolithic
generate_statement_irfunction has been broken down into the following logical components:mod.rs: Serves as the main entry point and orchestrator for statement generation.variable.rs: Handles variable declarations and complex initializations (including arrays and structs).assign.rs: Manages variable assignments and dereference-based stores.control.rs: Consolidates logic for control flow structures, includingifchains,whileloops, and jump statements (break,continue,return).io.rs: Encapsulates standard I/O logic forprint,println, and the recently addedinputstatement.asm.rs: Dedicated logic for processing and emitting inline assembly blocks.expr_stmt.rs: Handles statements that consist of a single expression.2. Logic Migration & Cleanup
gen_variable_ir,gen_if_ir, andgen_io_ir.truthy_to_i1(for boolean coercion) andmake_global_cstr(for string literal management), are now managed within their relevant modules or shared viamod.rs.3. Behavioral Consistency
generate_statement_irsignature remains stable to ensure zero impact on the rest of the compiler's pipeline.