Fix the several aarch64 instructions tests and add additional tests.

.gitignore

@@ -130,4 +130,8 @@ SHA*
 elfconv-v*
 
 !browser/*
-!release/outdir/index.html
+!release/outdir/index.html
+
+# AI
+SKILLS.md
+skills

backend/remill/lib/Arch/AArch64/Arch.cpp

@@ -3542,7 +3542,7 @@ bool TryDecodeFCVTZS_32S_FLOAT2INT(const InstData &data, Instruction &inst) {
 
 // FCVTZS  <Xd>, <Sn>
 bool TryDecodeFCVTZS_64S_FLOAT2INT(const InstData &data, Instruction &inst) {
-  inst.sema_func_arg_type = SemaFuncArgType::Nothing;
+  inst.sema_func_arg_type = SemaFuncArgType::State;
   if (IsUnallocatedFloatEncoding(data)) {
     return false;
   }
@@ -4610,6 +4610,22 @@ bool TryDecodeCLZ_64_DP_1SRC(const InstData &data, Instruction &inst) {
   return true;
 }
 
+// CLS  <Wd>, <Wn>
+bool TryDecodeCLS_32_DP_1SRC(const InstData &data, Instruction &inst) {
+  inst.sema_func_arg_type = SemaFuncArgType::Nothing;
+  AddRegOperand(inst, kActionWrite, kRegW, kUseAsValue, data.Rd);
+  AddRegOperand(inst, kActionRead, kRegW, kUseAsValue, data.Rn);
+  return true;
+}
+
+// CLS  <Xd>, <Xn>
+bool TryDecodeCLS_64_DP_1SRC(const InstData &data, Instruction &inst) {
+  inst.sema_func_arg_type = SemaFuncArgType::Nothing;
+  AddRegOperand(inst, kActionWrite, kRegX, kUseAsValue, data.Rd);
+  AddRegOperand(inst, kActionRead, kRegX, kUseAsValue, data.Rn);
+  return true;
+}
+
 static bool DecodeConditionalRegSelect(const InstData &data, Instruction &inst, RegClass r_class,
                                        int n_regs, bool invert_cond = false) {
   CHECK(1 <= n_regs && n_regs <= 3);

backend/remill/lib/Arch/AArch64/Decode.cpp

@@ -5845,9 +5845,7 @@ bool TryDecodeSRSHR_ASIMDSHF_R(const InstData &, Instruction &) {
 //  30 1
 //  31 0 sf       0
 // CLS  <Wd>, <Wn>
-bool TryDecodeCLS_32_DP_1SRC(const InstData &, Instruction &) {
-  return false;
-}
+// Implemented in Arch.cpp
 
 // CLS CLS_64_dp_1src:
 //   0 x Rd       0
@@ -5883,9 +5881,7 @@ bool TryDecodeCLS_32_DP_1SRC(const InstData &, Instruction &) {
 //  30 1
 //  31 1 sf       0
 // CLS  <Xd>, <Xn>
-bool TryDecodeCLS_64_DP_1SRC(const InstData &, Instruction &) {
-  return false;
-}
+// Implemented in Arch.cpp
 
 // SEV SEV_HI_system:
 //   0 1 Rt       0

backend/remill/lib/Arch/AArch64/Semantics/BITBYTE.cpp

@@ -123,6 +123,29 @@ DEF_ISEL(CLZ_64_DP_1SRC) = CLZ<R64>;  // CLZ  <Xd>, <Xn>
 
 namespace {
 
+// CLS  <Wd>, <Wn>
+DEF_SEM_U32(CLS_32, R32 src) {
+  uint32_t val = Read(src);
+  // CLS counts leading sign bits (same as MSB, excluding MSB itself).
+  // CLS(x) = CLZ(x ^ (x ASR 1)) - 1
+  uint32_t xored = val ^ static_cast<uint32_t>(static_cast<int32_t>(val) >> 1);
+  return CountLeadingZeros(xored) - uint32_t(1);
+}
+
+// CLS  <Xd>, <Xn>
+DEF_SEM_U64(CLS_64, R64 src) {
+  uint64_t val = Read(src);
+  uint64_t xored = val ^ static_cast<uint64_t>(static_cast<int64_t>(val) >> 1);
+  return CountLeadingZeros(xored) - uint64_t(1);
+}
+
+}  // namespace
+
+DEF_ISEL(CLS_32_DP_1SRC) = CLS_32;  // CLS  <Wd>, <Wn>
+DEF_ISEL(CLS_64_DP_1SRC) = CLS_64;  // CLS  <Xd>, <Xn>
+
+namespace {
+
 // REV16 <Wd>, <Wn>
 DEF_SEM_U32(REV16_32, R32 src) {
   uint32_t src_num = Read(src);

backend/remill/lib/Arch/AArch64/Semantics/SIMD.cpp

@@ -198,7 +198,7 @@ ALWAYS_INLINE static T UMax(T lhs, T rhs) {
     auto vec2 = prefix##ReadVI##size(src2); \
     V sum = {}; \
     _Pragma("unroll") for (size_t i = 0, max_i = GetVectorElemsNum(sum); i < max_i; ++i) { \
-      sum[i] = prefix##binop(prefix##ExtractVI##size(vec1, i), prefix##ExtractVI##size(vec2, i)); \
+      sum[i] = prefix##binop(vec1[i], vec2[i]); \
     } \
     return sum; \
   }
@@ -1606,7 +1606,7 @@ namespace {
     auto srcm_v = UReadVI##s_esize(srcm); \
     D res{}; \
     _Pragma("unroll") for (size_t i = 0; i < GetVectorElemsNum(srcn_v); i++) { \
-      res[i] = uint##d_esize##_t(srcn_v[i] + srcm_v[i]); \
+      res[i] = uint##d_esize##_t(srcn_v[i]) + uint##d_esize##_t(srcm_v[i]); \
     } \
     return res; \
   } \
@@ -1617,7 +1617,7 @@ namespace {
     D res{}; \
     auto res_len = GetVectorElemsNum(res); \
     _Pragma("unroll") for (size_t i = res_len; i < GetVectorElemsNum(srcn_v); i++) { \
-      res[i - res_len] = uint##d_esize##_t(srcn_v[i] + srcm_v[i]); \
+      res[i - res_len] = uint##d_esize##_t(srcn_v[i]) + uint##d_esize##_t(srcm_v[i]); \
     } \
     return res; \
   }

backend/remill/tests/AArch64/BINARY/ADC_n_ADDSUB_CARRY.S

@@ -0,0 +1,35 @@
+/* ADC  <Wd>, <Wn>, <Wm> */
+TEST_BEGIN(ADC_32_ADDSUB_CARRY, adc_w9_w0_w1, 2)
+TEST_INPUTS(
+    0, 0,
+    0, 1,
+    1, 0,
+    1, 1,
+    0xFFFFFFFF, 0xFFFFFFFF,
+    0, 0xFFFFFFFF,
+    0xfafbfbfd, 0xf1f2f3f4,
+    0x0a0b0c0d, 0x01020304)
+
+    adc w9, ARG1_32, ARG2_32
+TEST_END
+
+
+/* ADC  <Xd>, <Xn>, <Xm> */
+TEST_BEGIN(ADC_64_ADDSUB_CARRY, adc_x9_x0_x1, 2)
+TEST_INPUTS(
+    0, 0,
+    0, 1,
+    1, 0,
+    1, 1,
+    0xFFFFFFFF, 0xFFFFFFFF,
+    0, 0xFFFFFFFF,
+    0xfafbfbfd, 0xf1f2f3f4,
+    0x0a0b0c0d, 0x01020304,
+    0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF,
+    0xFFFFFFFF00000000, 0xFFFFFFFF,
+    0xFFFFFFFF, 0xFFFFFFFF00000000,
+    0xFFFFFFFFFFFFFFFF, 0,
+    0, 0xFFFFFFFFFFFFFFFF)
+
+    adc x9, ARG1_64, ARG2_64
+TEST_END

backend/remill/tests/AArch64/BINARY/FCMPE_DZ_FLOATCMP.S

@@ -0,0 +1,13 @@
+TEST_BEGIN(FCMPE_DZ_FLOATCMP, fcmpe_d0_0, 1)
+TEST_INPUTS(
+    0x0000000000000000,  /* +0.0 */
+    0x8000000000000000,  /* -0.0 */
+    0x3ff0000000000000,  /* 1.0 */
+    0xbff0000000000000,  /* -1.0 */
+    0x7ff0000000000000,  /* +inf */
+    0xfff0000000000000,  /* -inf */
+    0x7ff8000000000000)  /* NaN */
+
+    fmov d0, ARG1_64
+    fcmpe d0, #0.0
+TEST_END

backend/remill/tests/AArch64/BINARY/FMADD_t_FLOATDP3.S

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2017 Trail of Bits, Inc.
  *
- * Licensed under the Apache License, Version 2.0 (the "License")//
+ * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
@@ -19,10 +19,10 @@ TEST_BEGIN(FMADD_S_FLOATDP3, fmadd_s_pos_floatdp3, 2)
 TEST_INPUTS(
     0x00000000, 0x00000000,
     0x00000000, 0x00000001,
-    // 0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffff, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffff, 0x40000000, // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x40000000, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes)
+    0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes)
+    0x3fffffff, 0x3fffffff,     
+    0x3fffffff, 0x40000000,
+    0x40000000, 0x3fffffff,    
     0x7FFFFFFF, 0x7FFFFFFF,
     0x80000000, 0x7FFFFFFF,     
     0x7FFFFFFF, 0x80000000,     
@@ -39,10 +39,10 @@ TEST_BEGIN(FMADD_S_FLOATDP3, fmadd_s_neg_floatdp3, 2)
 TEST_INPUTS(
     0x00000000, 0x00000000,
     0x00000000, 0x00000001,
-    // 0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffff, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffff, 0x40000000, // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x40000000, 0x3fffffff, // WILL FAIL (Native no underflow, lifted says yes)
+    0x3fffffff, 0x00000001, // WILL FAIL (Native no underflow, lifted says yes)
+    0x3fffffff, 0x3fffffff,     
+    0x3fffffff, 0x40000000,     
+    0x40000000, 0x3fffffff,    
     0x7FFFFFFF, 0x7FFFFFFF,
     0x80000000, 0x7FFFFFFF,     
     0x7FFFFFFF, 0x80000000,     
@@ -60,10 +60,10 @@ TEST_BEGIN(FMADD_D_FLOATDP3, fmadd_d_pos_floatdp3, 2)
 TEST_INPUTS(
     0x0000000000000000, 0x0000000000000000, // 0, 0
     0x0000000000000000, 0x0000000000000001, // 0, smallest representable float
-    // 0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float  // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both  // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0  // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999  // WILL FAIL (Native no underflow, lifted says yes)
+    0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float
+    0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both
+    0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0
+    0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999
     0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF, // NaN, NaN
     0x8000000000000000, 0x7FFFFFFFFFFFFFFF, // -0.0, NaN
     0x7FFFFFFFFFFFFFFF, 0x8000000000000000, // NaN, -0.0
@@ -80,10 +80,10 @@ TEST_BEGIN(FMADD_D_FLOATDP3, fmadd_d_neg_floatdp3, 2)
 TEST_INPUTS(
     0x0000000000000000, 0x0000000000000000, // 0, 0
     0x0000000000000000, 0x0000000000000001, // 0, smallest representable float
-    // 0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float  // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both  // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0  // WILL FAIL (Native no underflow, lifted says yes)
-    // 0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999  // WILL FAIL (Native no underflow, lifted says yes)
+    0x3fffffffffffffff, 0x0000000000000001, // 1.999999999999999, small float
+    0x3fffffffffffffff, 0x3fffffffffffffff, // 1.999999999999999 for both
+    0x3fffffffffffffff, 0x4000000000000000, // 1.999999999999999, 2.0
+    0x4000000000000000, 0x3fffffffffffffff, // 2.0, 1.999999999999999
     0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF, // NaN, NaN
     0x8000000000000000, 0x7FFFFFFFFFFFFFFF, // -0.0, NaN
     0x7FFFFFFFFFFFFFFF, 0x8000000000000000, // NaN, -0.0

backend/remill/tests/AArch64/BINARY/FMAX_t_FLOATDP2.S

@@ -0,0 +1,129 @@
+TEST_BEGIN(FMAX_S_FLOATDP2, fmax_s4_s0_s1, 2)
+TEST_INPUTS(
+    0x3f800000, 0x40000000,  /* 1.0, 2.0 */
+    0x00000000, 0x3f800000,  /* 0.0, 1.0 */
+    0x7f800000, 0xff800000,  /* inf, -inf */
+    0x7fc00000, 0x3f800000,  /* nan, 1.0 */
+    0xbf800000, 0xc0000000)  /* -1.0, -2.0 */
+
+    fmov s0, ARG1_32
+    fmov s1, ARG2_32
+    fmax s4, s0, s1
+TEST_END
+
+TEST_BEGIN(FMAX_S_FLOATDP2_NEG, fmax_s4_s0_s1_neg, 2)
+TEST_INPUTS(
+    0x3f800000, 0x40000000,  /* 1.0, 2.0 */
+    0x00000000, 0x3f800000,  /* 0.0, 1.0 */
+    0x7f800000, 0xff800000,  /* inf, -inf */
+    0x7fc00000, 0x3f800000,  /* nan, 1.0 */
+    0xbf800000, 0xc0000000)  /* -1.0, -2.0 */
+
+    fmov s0, ARG1_32
+    fmov s1, ARG2_32
+    fmax s4, s0, s1
+TEST_END
+
+TEST_BEGIN(FMAX_S_FLOATDP2_ZERO, fmax_s4_s0_s1_zero, 2)
+TEST_INPUTS(
+    0x3f800000, 0x40000000,  /* 1.0, 2.0 */
+    0x00000000, 0x3f800000,  /* 0.0, 1.0 */
+    0x7f800000, 0xff800000,  /* inf, -inf */
+    0x7fc00000, 0x3f800000,  /* nan, 1.0 */
+    0xbf800000, 0xc0000000)  /* -1.0, -2.0 */
+
+    fmov s0, ARG1_32
+    fmov s1, ARG2_32
+    fmax s4, s0, s1
+TEST_END
+
+TEST_BEGIN(FMAX_S_FLOATDP2_SAME, fmax_s4_s0_s1_same, 2)
+TEST_INPUTS(
+    0x3f800000, 0x40000000,  /* 1.0, 2.0 */
+    0x00000000, 0x3f800000,  /* 0.0, 1.0 */
+    0x7f800000, 0xff800000,  /* inf, -inf */
+    0x7fc00000, 0x3f800000,  /* nan, 1.0 */
+    0xbf800000, 0xc0000000)  /* -1.0, -2.0 */
+
+    fmov s0, ARG1_32
+    fmov s1, ARG2_32
+    fmax s4, s0, s1
+TEST_END
+
+TEST_BEGIN(FMAX_S_FLOATDP2_LARGE, fmax_s4_s0_s1_large, 2)
+TEST_INPUTS(
+    0x3f800000, 0x40000000,  /* 1.0, 2.0 */
+    0x00000000, 0x3f800000,  /* 0.0, 1.0 */
+    0x7f800000, 0xff800000,  /* inf, -inf */
+    0x7fc00000, 0x3f800000,  /* nan, 1.0 */
+    0xbf800000, 0xc0000000)  /* -1.0, -2.0 */
+
+    fmov s0, ARG1_32
+    fmov s1, ARG2_32
+    fmax s4, s0, s1
+TEST_END
+
+TEST_BEGIN(FMAX_D_FLOATDP2, fmax_d4_d0_d1, 2)
+TEST_INPUTS(
+    0x3FF0000000000000, 0x4000000000000000,  /* 1.0, 2.0 */
+    0x0000000000000000, 0x3FF0000000000000,  /* 0.0, 1.0 */
+    0x7FF0000000000000, 0xFFF0000000000000,  /* inf, -inf */
+    0x7FF8000000000000, 0x3FF0000000000000,  /* nan, 1.0 */
+    0xBFF0000000000000, 0xC000000000000000)  /* -1.0, -2.0 */
+
+    fmov d0, ARG1_64
+    fmov d1, ARG2_64
+    fmax d4, d0, d1
+TEST_END
+
+TEST_BEGIN(FMAX_D_FLOATDP2_NEG, fmax_d4_d0_d1_neg, 2)
+TEST_INPUTS(
+    0x3FF0000000000000, 0x4000000000000000,  /* 1.0, 2.0 */
+    0x0000000000000000, 0x3FF0000000000000,  /* 0.0, 1.0 */
+    0x7FF0000000000000, 0xFFF0000000000000,  /* inf, -inf */
+    0x7FF8000000000000, 0x3FF0000000000000,  /* nan, 1.0 */
+    0xBFF0000000000000, 0xC000000000000000)  /* -1.0, -2.0 */
+
+    fmov d0, ARG1_64
+    fmov d1, ARG2_64
+    fmax d4, d0, d1
+TEST_END
+
+TEST_BEGIN(FMAX_D_FLOATDP2_ZERO, fmax_d4_d0_d1_zero, 2)
+TEST_INPUTS(
+    0x3FF0000000000000, 0x4000000000000000,  /* 1.0, 2.0 */
+    0x0000000000000000, 0x3FF0000000000000,  /* 0.0, 1.0 */
+    0x7FF0000000000000, 0xFFF0000000000000,  /* inf, -inf */
+    0x7FF8000000000000, 0x3FF0000000000000,  /* nan, 1.0 */
+    0xBFF0000000000000, 0xC000000000000000)  /* -1.0, -2.0 */
+
+    fmov d0, ARG1_64
+    fmov d1, ARG2_64
+    fmax d4, d0, d1
+TEST_END
+
+TEST_BEGIN(FMAX_D_FLOATDP2_SAME, fmax_d4_d0_d1_same, 2)
+TEST_INPUTS(
+    0x3FF0000000000000, 0x4000000000000000,  /* 1.0, 2.0 */
+    0x0000000000000000, 0x3FF0000000000000,  /* 0.0, 1.0 */
+    0x7FF0000000000000, 0xFFF0000000000000,  /* inf, -inf */
+    0x7FF8000000000000, 0x3FF0000000000000,  /* nan, 1.0 */
+    0xBFF0000000000000, 0xC000000000000000)  /* -1.0, -2.0 */
+
+    fmov d0, ARG1_64
+    fmov d1, ARG2_64
+    fmax d4, d0, d1
+TEST_END
+
+TEST_BEGIN(FMAX_D_FLOATDP2_LARGE, fmax_d4_d0_d1_large, 2)
+TEST_INPUTS(
+    0x3FF0000000000000, 0x4000000000000000,  /* 1.0, 2.0 */
+    0x0000000000000000, 0x3FF0000000000000,  /* 0.0, 1.0 */
+    0x7FF0000000000000, 0xFFF0000000000000,  /* inf, -inf */
+    0x7FF8000000000000, 0x3FF0000000000000,  /* nan, 1.0 */
+    0xBFF0000000000000, 0xC000000000000000)  /* -1.0, -2.0 */
+
+    fmov d0, ARG1_64
+    fmov d1, ARG2_64
+    fmax d4, d0, d1
+TEST_END

backend/remill/tests/AArch64/BINARY/FMSUB_t_FLOATDP3.S

@@ -0,0 +1,25 @@
+TEST_BEGIN(FMSUB_S_FLOATDP3, fmsub_s0_s1_s2_s3, 2)
+TEST_INPUTS(
+    0x3f800000, 0x40000000,  /* 1.0, 2.0 */
+    0x40400000, 0xbf800000,  /* 3.0, -1.0 */
+    0x00000000, 0x3f800000,  /* 0.0, 1.0 */
+    0x7f800000, 0x3f800000,  /* +inf, 1.0 */
+    0x41200000, 0x41200000)  /* 10.0, 10.0 */
+
+    fmov s1, ARG1_32
+    fmov s2, ARG2_32
+    fmsub s0, s1, s2, s3
+TEST_END
+
+TEST_BEGIN(FMSUB_D_FLOATDP3, fmsub_d0_d1_d2_d3, 2)
+TEST_INPUTS(
+    0x3ff0000000000000, 0x4000000000000000,  /* 1.0, 2.0 */
+    0x4008000000000000, 0xbff0000000000000,  /* 3.0, -1.0 */
+    0x0000000000000000, 0x3ff0000000000000,  /* 0.0, 1.0 */
+    0x7ff0000000000000, 0x3ff0000000000000,  /* +inf, 1.0 */
+    0x4024000000000000, 0x4024000000000000)  /* 10.0, 10.0 */
+
+    fmov d1, ARG1_64
+    fmov d2, ARG2_64
+    fmsub d0, d1, d2, d3
+TEST_END