DLab is an implementation-oriented digital design course offered by National Yang Ming Chiao Tung University (NYCU). Every lab requires participants to independently complete the RTL and corresponding testbench, covering the entire process from understanding specifications to design implementation and functional verification. The development board I used in the course was the Digilent ZedBoard, featuring the Zynq-7000 SoC platform that combines an ARM Cortex-A9 with an FPGA (this lab focused solely on the PL section) using AMD Xilinx Vivado for design and verification.
Over the course of the semester, I completed 10 labs. The content covered Verilog RTL coding, FSM design, datapath and controller planning, memory (SRAM) and peripheral module integration, and the establishment of complete testbench writing and verification flows. Starting from simple behavioral descriptions, I eventually progressed to considering architectural choices, resource utilization, and timing constraints based on specifications, gradually developing the ability to transform abstract requirements into synthesizable circuits. Regarding verification, in addition to checking functional correctness through simulation, I also learned to use Vivado ILA (Integrated Logic Analyzer) to observe internal signals during hardware testing, which assisted in debugging and understanding actual hardware behavior.
Through the training in DLab, my capabilities in digital design have grown significantly. I can now conceptualize overall architectures based on problem specifications and make trade-offs and optimizations regarding power, performance, and area (PPA). Successfully downloading designs onto the FPGA and seeing them run also made me realize that electrical and physical factors still influence the gap between simulation and real circuits; seeing the circuits operate successfully on hardware provided a great sense of achievement. This course has significantly improved my RTL coding and testbench writing skills and established a solid understanding of the complete digital system design and verification flow on FPGAs.
| Labs | Descriptions |
|---|---|
| Lab1 | Sequential Binary Multiplier |
| Lab2 | 3x3 Matrix Multiplier |
| Lab3 | Simple I/O Control Circuit |
| Lab4 | UART I/O Circuit |
| Lab5 | Sieve Algorithm & Standard 1602 Character LCD Display |
| Lab7 | 4x4 Pipelined Matrix Multiplier |
| Lab8 | MD5 Password Cracking Circuit |
| Lab9 | Correlation Filter Circuit |
| Lab10 | VGA Video Interface Circuit |
