Be more verbose why exactly device tree parsing failed

Documentation/devicetree/bindings/xlnx,v-hdmi-rx-ss.txt

@@ -6,13 +6,13 @@ V4L2 video-capture sub-device for the Xilinx Video IP Pipeline device
 (xilinx-vipp).
 
 There are 2 optional HDCP cores that can be included in the IP configuration.
-Below provided sample device tree depicts the configuration when both cores are 
-included. If an optional core is included then corresponding entries for the 
+Below provided sample device tree depicts the configuration when both cores are
+included. If an optional core is included then corresponding entries for the
 core parameters (interrupts, key-management block address) must be included in
 the device tree
 
 Note: If HDCP cores are included in the design, the user must provide valid
-	  HDCP keys for the encryption to work. 
+	  HDCP keys for the encryption to work.
 
 Refer to xlnx,vphy.txt for the phy specifics.
 
@@ -25,71 +25,92 @@ Required Properties:
 			hdcp1x. [Optional]
  - interrupts-parent: phandle for interrupt controller.
  - interrupts: Interrupt numbers for mandatory and optional blocks
- - interrupt-names: Identification string that binds irq number to block 
+ - interrupt-names: Identification string that binds irq number to block
 		generating the interrupt
-		"hdmirx": interrupt for rx subcore [always present]
-		"hdcp1x": interrupt for hdcp1.4 core [optional]
-		"hdcp1x-timer": interrupt for hdcp1.4 timer [present if hdcp1x is 
-			included]
-		"hdcp22": interrupt for hdcp22 core [optional]
-		"hdcp22-timer": interrupt for hdcp2.2 timer [present if hdcp22 is
-			included]
-
- - clocks: phandle for axi-lite, video stream
- - clock-names: The identification string, "axi-lite", is always required for
-                the axi-lite clock, "video" is always required for video stream
-				clock
-
- - phys: phandle for phy lanes registered for hdmi protocol. HDMI always 
+		"irq": interrupt for tx subcore [always present]
+		"hdcp14_irq": interrupt for hdcp1.4 core [optional - present if hdcp1x
+		is included]
+		"hdcp14_timer_irq": interrupt for hdcp1.4 timer [optional - present if
+		hdcp1x is included]
+		"hdcp22_irq": interrupt for hdcp22 core [optional - present if hdcp22
+		is included]
+		"hdcp22_timer_irq": interrupt for hdcp2.2 timer [optional - present if
+		hdcp22 is included]
+
+ - clocks: phandle of all the clocks required by IP are listed here.
+ - clock-names: names of all the clocks required by IP are listed here.
+          NOTE: Auto generated DT is providing all the clock names and handles
+          reuired by the IP.
+          NOTE: Below are the identification string that are always required.
+              "s_axi_cpu_aclk", is always required for the axi-lite clock
+              "s_axis_video_aclk" is always required for video stream clock
+
+ - phys: phandle for phy lanes registered for hdmi protocol. HDMI always
          require 3 lanes
  - phy-names: The identification string, "hdmi-phy0" and so on
- 
+
  - xlnx,input-pixels-per-clock: IP configuration for samples/clk (2, 4)
          Note: Only 2 is supported at this time
- - xlnx,edid-ram-size: Denotes amount of BRAM allocated for EDID in IP 
+ - xlnx,max-bits-per-component: The data width per video component (8,10,12,16)
+         Note: Only 8 & 10 is supported at this time
+ - xlnx,edid-ram-size: Denotes amount of BRAM allocated for EDID in IP
  - xlnx,include-hdcp-1-4: Boolean parameter that denotes if hdcp14 is included.
 		If present indicates inclusion of the optional core
  - xlnx,include-hdcp-2-2: Boolean parameter that denotes if hdcp22 is included.
 		If present indicates inclusion of the optional core
+ - xlnx,audio-enabled: Boolean parameter to convey that design has audio
+		functionality.
+		If present, indicates optional audio core needed for audio
+		usecase is included.
+ - xlnx,snd-pcm: Reference to audio formatter block. Add this if, audio formatter
+		is going to be used for HDMI audio.
+		Needed only if "xlnx,audio-enabled" is included.
  - ports: Video ports, using the DT bindings defined in ../video-interfaces.txt.
           The Rx only has an output port (0).
- 
+
 ==Example==
 If hdcp1.4 is included in the design then key management block node should be
 added to the device tree
 
-	hdmi_input_hdcp_keymngmt_blk_top_1: hdcp_keymngmt_blk_top@a0270000 {
+	hdcp_keymngmt_blk_1: hdcp_keymngmt_blk_top@88000000 {
+		clock-names = "s_axi_aclk", "m_axis_aclk";
+		clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
 		compatible = "xlnx,hdcp-keymngmt-blk-top-1.0";
-		reg = <0x0 0xa0270000 0x0 0x10000>;
+		reg = <0x0 0x88000000 0x0 0x10000>;
 	};
 
-	hdmi_input_v_hdmi_rx_ss_0: v_hdmi_rx_ss@a0000000 {
+	v_hdmi_rx_ss: v_hdmi_rx_ss@80000000 {
 		compatible = "xlnx,v-hdmi-rx-ss-3.1";
 		reg = <0x0 0xa0000000 0x0 0x100000>, <0x0 0xa0270000 0x0 0x10000>;
-		reg-names = "hdmi-rxss", "hdcp1x-keymngmt";	
+		reg-names = "hdmi-rxss", "hdcp1x-keymngmt";
 		interrupt-parent = <&gic>;
-		interrupts = <0 91 4>, <0 108 4>, <0 109 4>, <0 110 4>, <0 111 4>;
-		interrupt-names = "hdmirx", "hdcp1x", "hdcp1x-timer", "hdcp22", "hdcp22-timer";
-		clocks = <&vid_s_axi_clk>, <&vid_stream_clk>;
-		clock-names = "axi-lite", "video";
+		interrupts = <0 90 4 0 104 4 0 105 4 0 108 4 0 109 4>;
+		interrupt-names = "irq", "hdcp14_irq", "hdcp14_timer_irq", "hdcp22_irq", "hdcp22_timer_irq";
+		clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk";
+		clocks = <&zynqmp_clk 71>, <&misc_clk_1>, <&zynqmp_clk 71>, <&misc_clk_2>, <&zynqmp_clk 72>;
 		phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
 		phys = <&vphy_lane0 0 1 1 0>, <&vphy_lane1 0 1 1 0>, <&vphy_lane2 0 1 1 0>;
-	
+
 		xlnx,input-pixels-per-clock = <0x2>;
+		xlnx,max-bits-per-component = <0xa>;
 		xlnx,edid-ram-size = <0x100>;
 		xlnx,include-hdcp-1-4;
 		xlnx,include-hdcp-2-2;
-
+		xlnx,audio-enabled;
+		xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>;
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			port@0 {
 				reg = <0>;
-	
+
 				/* HDMI RX SS -> FB-WR */
 				hdmi_rxss_out: endpoint {
 					remote-endpoint = <&vcap_hdmi_in>;
 				};
 			};
-		};			
+		};
 	};
+
+	Documentation of "audio_ss_0_audio_formatter_0" node is located
+	at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt

Documentation/devicetree/bindings/xlnx,v-hdmi-tx-ss.txt

@@ -5,21 +5,21 @@ a HDMI Transmitter. xilinx_drm_hdmi.c implements a DRM/KMS driver
 encoder/connector interface in the output pipeline.
 
 There are 2 optional HDCP cores that can be included in the IP configuration.
-Below provided sample device tree depicts the configuration when both cores are 
-included. If an optional core is included then corresponding entries for the 
+Below provided sample device tree depicts the configuration when both cores are
+included. If an optional core is included then corresponding entries for the
 core parameters (interrupts, key-management block address) must be included in
 the device tree
 
 Note: If HDCP cores are included in the design, the user must provide valid
-	  HDCP keys for the encryption to work. 
+	  HDCP keys for the encryption to work.
 
 Note: This version of the driver interfaces with the new Xilinx DRM component
 	  framework and is not backward compatible with the earlier encoder-slave
 	  interface. As such compatibility string has been reved up to indicate the
 	  new interface.
 
 Refer to xlnx,vphy.txt for the phy specifics.
-	  
+
 Required properties:
  - compatible: Should be "xlnx,v-hdmi-tx-ss-3.1".
  - reg: Base address and size of the IP core and hdcp1x key management block
@@ -30,27 +30,35 @@ Required properties:
 
  - interrupts-parent: phandle for interrupt controller.
  - interrupts: Interrupt numbers for mandatory and optional blocks
- - interrupt-names: Identification string that binds irq number to block 
+ - interrupt-names: Identification string that binds irq number to block
 		generating the interrupt
-		"hdmitx": interrupt for tx subcore [always present]
-		"hdcp1x": interrupt for hdcp1.4 core [optional]
-		"hdcp1x-timer": interrupt for hdcp1.4 timer [present if hdcp1x is 
-			included]
-		"hdcp22": interrupt for hdcp22 core [optional]
-		"hdcp22-timer": interrupt for hdcp2.2 timer [present if hdcp22 is
-			included]
-
- - clocks: phandle for axi-lite, video stream, tmds and retimer clock
- - clock-names: The identification string for various clock inputs
-				"axi-lite", is always required for the axi-lite clock
-				"video" is always required for video stream clock 
-				"txref-clk" is always required for tmds clock
-				"retimer-clk" is required only when retimer is being used
-
- - phys: phandle for phy lanes registered for hdmi protocol. HDMI always 
+		"irq": interrupt for tx subcore [always present]
+		"hdcp14_irq": interrupt for hdcp1.4 core [optional - present if hdcp1x
+		is included]
+		"hdcp14_timer_irq": interrupt for hdcp1.4 timer [optional - present if
+		hdcp1x is included]
+		"hdcp22_irq": interrupt for hdcp22 core [optional - present if hdcp22
+		is included]
+		"hdcp22_timer_irq": interrupt for hdcp2.2 timer [optional - present if
+		hdcp22 is included]
+
+ - clocks: phandle of all the clocks required by IP are listed here.
+ - clock-names: names of all the clocks required by IP are listed here.
+          NOTE: Auto generated DT is providing all the clock names and handles
+          reuired by the IP.
+          NOTE: Below are the identification string that are always required.
+              "s_axi_cpu_aclk", is always required for the axi-lite clock
+              "s_axis_video_aclk" is always required for video stream clock
+              "txref-clk" is always required for tmds clock
+              "retimer-clk" is required only when retimer is being used
+          NOTE: "txref-clk" and "retimer-clk" needs to be explicitly added in
+          the list of clock-names and its phandle in clocks as its derived by
+          external clock.
+
+ - phys: phandle for phy lanes registered for hdmi protocol. HDMI always
          require 3 lanes
  - phy-names: The identification string, "hdmi-phy0" and so on
- 
+
  - xlnx,input-pixels-per-clock: IP configuration for samples/clk (2, 4)
          Note: Only 2 is supported at this time
  - xlnx,max-bits-per-component: The data width per video component (8,10,12,16)
@@ -59,11 +67,22 @@ Required properties:
 		If present indicates inclusion of the optional core
  - xlnx,include-hdcp-2-2: Boolean parameter that denotes if hdcp22 is included.
 		If present indicates inclusion of the optional core
- - xlnx,hdcp-authenticate: Flag to enable/disable hdcp authentication. 
+ - xlnx,hdcp-authenticate: Flag to enable/disable hdcp authentication.
 		Applicable when either hdcp14 or hdcp22 is included in the design
  - xlnx,hdcp-encrypt: Flag to enable/disable stream encryption
  		Applicable when either hdcp14 or hdcp22 is included in the design
-
+ - xlnx,audio-enabled: Boolean parameter to convey that design has audio
+                functionality.
+		If present, indicates optional audio core needed for audio
+		usecase is included.
+ - xlnx,aes_parser: Alias to audio channel status extractor block.
+		Needed only if "xlnx,audio-enabled" is included.
+ - xlnx,snd-pcm: Reference to audio formatter block. Add this if, audio formatter
+                is going to be used for HDMI audio.
+		Needed only if "xlnx,audio-enabled" is included.
+ - xlnx,xlnx-hdmi-acr-ctrl: Alias to audio clock recovery block.
+		Needed only if "xlnx,audio-enabled" is included.
+
 Sub-Node Properties:
 	The device tree will need to include a sub-node for the encoder endpoint
 	interface. This port will bind the hdmi encoder with the crtc being used
@@ -82,21 +101,29 @@ depending on the TX clock line rate. Tested with dp159.c driver.
 If hdcp1.4 is included in the design then key management block node should be
 added to the device tree
 
-	hdmi_output_hdcp_keymngmt_blk_top_0: hdcp_keymngmt_blk_top@a0280000 {
+	hdcp_keymngmt_blk_0: hdcp_keymngmt_blk_top@90000000 {
+		clock-names = "s_axi_aclk", "m_axis_aclk";
+		clocks = <&zynqmp_clk 71>, <&misc_clk_0>;
 		compatible = "xlnx,hdcp-keymngmt-blk-top-1.0";
-		reg = <0x0 0xa0280000 0x0 0x10000>;
+		reg = <0x0 0x90000000 0x0 0x10000>;
 	};
 
-	hdmi_output_v_hdmi_tx_ss_0: v_hdmi_tx_ss@a0080000 {
+	hdmi_acr_ctrl_0: hdmi_acr_ctrl@a0059000 {
+		/* This is a place holder node for a custom IP, user may need to update the entries */
+		compatible = "xlnx,hdmi-acr-ctrl-1.0";
+		reg = <0x0 0xa0059000 0x0 0x1000>;
+	};
+
+	v_hdmi_tx_ss: v_hdmi_tx_ss@80080000 {
 		compatible = "xlnx,v-hdmi-tx-ss-3.1";
 		reg = <0x0 0xa0080000 0x0 0x80000>, <0x0 0xa0280000 0x0 0x10000>;
-		reg-names = "hdmi-txss", "hdcp1x-keymngmt";			
+		reg-names = "hdmi-txss", "hdcp1x-keymngmt";
 		interrupt-parent = <&gic>;
-		interrupts = <0 93 4>, <0 104 4>, <0 105 4>, <0 106 4>, <0 107 4>;
-		interrupt-names = "hdmitx", "hdcp1x", "hdcp1x-timer", "hdcp22", "hdcp22-timer";
-		
-		clocks = <&axi_lite_clk>, <&axi_stream_clk>, <&si5324 0>, <&dp159>;
-		clock-names = "axi-lite", "video", "txref-clk", "retimer-clk";
+		interrupts = <0 91 4 0 106 4 0 107 4 0 110 4 0 111 4>;
+		interrupt-names = "irq", "hdcp14_irq", "hdcp14_timer_irq", "hdcp22_irq", "hdcp22_timer_irq";
+
+		clock-names = "s_axi_cpu_aclk", "link_clk", "s_axis_audio_aclk", "video_clk", "s_axis_video_aclk", "txref-clk", "retimer-clk";
+		clocks = <&zynqmp_clk 71>, <&misc_clk_1>, <&zynqmp_clk 71>, <&misc_clk_2>, <&zynqmp_clk 72>, <&si5324 0>, <&dp159>;
 		phy-names = "hdmi-phy0", "hdmi-phy1", "hdmi-phy2";
 		phys = <&vphy_lane0 0 1 1 1>, <&vphy_lane1 0 1 1 1>, <&vphy_lane2 0 1 1 1>;
 
@@ -107,6 +134,9 @@ added to the device tree
 		/* settings for HDCP */
 		xlnx,hdcp-authenticate = <0x1>;
 		xlnx,hdcp-encrypt = <0x1>;
+		xlnx,audio-enabled;
+		xlnx,xlnx-hdmi-acr-ctrl = <&hdmi_acr_ctrl_0>;
+		xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>;
 
 		ports {
 			#address-cells = <1>;
@@ -134,3 +164,6 @@ added to the device tree
 			};
 		};
 	};
+
+	Documentation of "audio_ss_0_audio_formatter_0" node is located
+	at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt