Pinned Loading

1. CPM-UVM-Verification CPM-UVM-Verification Public

   UVM testbench for Configurable Packet Modifier (CPM): RAL, virtual sequences, functional coverage, scoreboard, SVA.

   SystemVerilog

2. Timer-Peripheral-Verification Timer-Peripheral-Verification Public

   ASIC verification environment for a 32-bit programmable timer, featuring SystemVerilog UVM-style architecture, SVA, Shadow Memory logic for cross-coverage, and weighted constrained-random stimulus.

   SystemVerilog

3. divide-by-3-clock-divider divide-by-3-clock-divider Public

   SystemVerilog divide-by-3 clock divider with 50% duty cycle using dual counter architecture

   SystemVerilog

4. first-signal-detector first-signal-detector Public

   SystemVerilog first-arrival signal detector with lock mechanism - captures and preserves the first detected signal pattern

   SystemVerilog

5. hangman-game hangman-game Public

   Hangman game based on 'Pygame' module.

   Python

6. 8bit-full-adder 8bit-full-adder Public

   Implementation of 8-bit Full Adder using 1-bit Full Adders in Verilog

   Verilog