Verification Project: 32-bit Timer Peripheral

1. Project Overview

This project is a SystemVerilog-based verification environment for a 32-bit Timer Peripheral. The goal is to verify the design against the Requirements Traceability Matrix (RTM) R1-R6, ensuring protocol compliance, functional correctness, and corner-case handling.

The environment uses a layered testbench architecture (Generator -> Driver -> Monitor -> Scoreboard/Coverage).

2. File Structure & Architecture

Verification Plan Execution & Closure

The verification strategy and requirements mapping for this project are defined in the Verification Plan (plan/verification_plan.pdf). All planned verification artifacts (assertions, directed tests, random regression, scoreboard checks, and functional coverage) were fully implemented and executed. Evidence of successful execution and verification closure is provided in:

• logs/sim.log – simulation transcript showing test execution and PASS results
• coverage/coverage.txt – functional coverage report demonstrating 100% coverage closure

Design Under Test (DUT)

• timer_periph.sv: The synthesizable RTL logic for the 32-bit timer.

Verification Environment

• timer_top.sv: The top-level module connecting the Testbench and DUT.
• design_params_pkg.sv: Defines constants used throughout the project (e.g., P_ADDR_WIDTH).
• timer_pkg.sv: Package for type definitions. Exports design_params_pkg contents.
• timer_pkt.sv: Defines the bus_trans class (transaction definition).
• timer_if.sv: Interface definition including SVA Assertions (R1 Protocol checks).
• timer_generator.sv: Stimulus Generation. Contains directed tests and constrained-random regression tasks.
• timer_driver.sv: Drives pin-level transactions to the DUT based on generator requests.
• timer_monitor.sv: Observes bus activity and broadcasts transactions to the Scoreboard and Coverage.
• timer_scoreboard.sv: Checking Logic. Implements the reference model and validates flag behavior (R4, R5).
• timer_coverage.sv: Functional Coverage. Implements "Shadow Memory" logic to cross-cover Load Values with Reload Modes.

3. Implemented Tests

The timer_generator.sv file contains the following test scenarios, directly traceable to the Test Plan:

Test Name	Type	Purpose	Req ID
timer_sanity_test	Directed	Smoke Test. basic read/write and short countdown to ensure DUT is alive.	R1, R2
timer_load_0_test	Directed	Corner Case. Writes 0 to LOAD to verify it translates to 1 cycle.	R3
timer_reload_test	Directed	Mode Verification. Verifies Auto-Reload functionality without software intervention.	R6
timer_status_test	Directed	Flag Verification. Checks "Sticky" behavior, Clear-on-Read, and Clear-on-Write.	R5
timer_random_regression	Random	Coverage Closure. Uses weighted distribution to target Corner Cases (Max/Min Load) and Cross Coverage.	All

4. Key Verification Features

• Shadow Memory (in timer_coverage.sv): Solves the temporal separation problem between Mode configuration and Load operations. A local copy of the RELOAD_EN bit is maintained to allow accurate cross-coverage sampling.
• Weighted Randomization: Uses dist constraints to force corner cases (0x0000, 0xFFFF) to occur at higher probability, significantly optimizing coverage closure time.

5. How to Run

(Using QuestaSim)

1. Compile the Design and Verification files:

   vlib work
   vlog +acc timer_pkg.sv timer_if.sv timer_periph.sv timer_top.sv

2. Run the Simulation:

   vsim -c timer_top -do "run -all"

3. View Coverage Report:

   coverage report -detail -cvg