The aim of this project was to build a running prototype of RISC-V processor i.e. RV32IF on FPGA. My implementation of RV32IF can be programmed using C to perform any float operation and display the result on computer through JTAG. This project was done using Altera DE 1 FPGA board and the language used was verilog HDL.
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Implementation of RV32IF using verilog HDL and tested on Altera DE1 board
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